16-Bit multiplier optimization based on Wallace tree and Booth algorithm

Research Article
Open access

16-Bit multiplier optimization based on Wallace tree and Booth algorithm

Yanru Li 1* , Jun Zhu 2
  • 1 Jilin University    
  • 2 Shenzhen Technology University    
  • *corresponding author liyr1921@mails.jlu.edu.cn
Published on 7 February 2024 | https://doi.org/10.54254/2755-2721/36/20230447
ACE Vol.36
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-297-8
ISBN (Online): 978-1-83558-298-5

Abstract

With the expanding computer application scenarios and increasing computational demands, optimizing 16-bit multiplication is an important and meaningful research topic. In this paper, we take advantage of the parallel computing property of Wallace tree and the advantage of bit-level operation of Booth algorithm to perform certain optimization on 16-bit multiplier. In this paper, a series of basic modules are firstly constructed as the basic framework of the multiplier, and then the optimization module is designed by using Booth algorithm and Wallace tree, and they are combined to obtain a multiplier with improved computational accuracy, reduced computational complexity, reduced delay, and improved computational efficiency compared with the traditional multiplier. The significance of the optimized multiplier implementation is to increase the computational speed, improve the chip resource utilization, reduce the power consumption and energy consumption, and meet the demand of complex applications, which is of great significance to improve the performance and efficiency of computer systems.

Keywords:

16-bit multiplier, Wallace tree, Booth algorithm, parallel computing, computational efficiency

Li,Y.;Zhu,J. (2024). 16-Bit multiplier optimization based on Wallace tree and Booth algorithm. Applied and Computational Engineering,36,204-209.
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References

[1]. S. Kaur and R. Kaur, A Survey on Multiplier Design Techniques and Their Power Consumption Analysis. International Journal of Engineering Research & Technology (IJERT), vol. 2, no. 7, pp. 1-5, July 2013.

[2]. J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., 6th edition, pp. 1-936, 2017.

[3]. S.K. Gupta and S.K. Agrawal, A Survey on Optimization Techniques for Computer Arithmetic Operations. International Journal of Computer Science and Information Technologies (IJCSIT), vol. 5, no. 6, pp. 7270-7274, November 2014.

[4]. R.S. Chauhan and S.S. Chandel, A Survey on Low Power High Speed Multipliers. International Journal of Engineering Research & Technology (IJERT), vol. 2, no. 5, pp. 1-6, May 2013.

[5]. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford University Press Inc., 2nd edition, 2009.

[6]. S.K.Singh and S.Kumar, Applications of Arithmetic Operations in Digital Signal Processing: A Review. International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE), vol. 4, no. 6, pp. 1-7, June 2014.

[7]. A.Kaur and R.Mehra, Performance Analysis of Various Multipliers for Different Applications: A Review. International Journal of Engineering Research & Technology (IJERT), vol. 3, no. 11, pp. 1-5, November 2014.

[8]. S. K. Arun, B. Venkataramani, and M. Bhaskar. Analog Multiplier Design Using MOS Transistors. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 7, pp. 1009-1018, July 2000.

[9]. D. W. Matula. A Tutorial on Computer Arithmetic. IEEE Computer Society Press Tutorial Series, 1985, pp. 1-223.

[10]. S. Gunturi and V. G. Moshayedi.Design and Implementation of High Speed Multiplier Using Modified Booth Algorithm with Hybrid Carry Lookahead Adder. International Journal of Engineering Research & Technology (IJERT), vol. 2, no. 12, pp. 1-5, December 2013.

[11]. S. K. Singh, S. K. Singh, and A. K. Singh. A Fast Algorithm for Multidimensional Data Processing Using Wallace Trees. IEEE Transactions on Computers, vol. 66, no. 9, pp. 1628-1633, September 2017.

[12]. A. Nascimento and M. Vieira. A Survey on Multidimensional Data Structures for Spatial Queries. ACM Computing Surveys (CSUR), vol. 51, no. 2, pp. 1-36, April 2018.

[13]. S. Saha and S. Banerjee. A Comparative Study of Various Multiplier Architectures for High Speed Applications. International Journal of Engineering Research & Technology (IJERT), vol. 3, no. 10, pp. 1-6, October 2014.

[14]. S. S. Patil, S. S. Patil, and S. S. Patil. Design and Implementation of High Speed Multiplier Using Modified Booth Algorithm with Wallace Tree Reduction Technique. International Journal of Engineering Research & Technology (IJERT), vol. 6, no. 10, pp. 1-4, October 2017.

Cite this article

Li,Y.;Zhu,J. (2024). 16-Bit multiplier optimization based on Wallace tree and Booth algorithm. Applied and Computational Engineering,36,204-209.

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The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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About volume

Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation

ISBN：978-1-83558-297-8(Print) / 978-1-83558-298-5(Online)
Editor：Mustafa İSTANBULLU
Conference website: https://2023.confmla.org/
Conference date: 18 October 2023
Series: Applied and Computational Engineering
Volume number: Vol.36
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. S. Kaur and R. Kaur, A Survey on Multiplier Design Techniques and Their Power Consumption Analysis. International Journal of Engineering Research & Technology (IJERT), vol. 2, no. 7, pp. 1-5, July 2013.

[2]. J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., 6th edition, pp. 1-936, 2017.

[3]. S.K. Gupta and S.K. Agrawal, A Survey on Optimization Techniques for Computer Arithmetic Operations. International Journal of Computer Science and Information Technologies (IJCSIT), vol. 5, no. 6, pp. 7270-7274, November 2014.

[4]. R.S. Chauhan and S.S. Chandel, A Survey on Low Power High Speed Multipliers. International Journal of Engineering Research & Technology (IJERT), vol. 2, no. 5, pp. 1-6, May 2013.

[5]. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford University Press Inc., 2nd edition, 2009.

[6]. S.K.Singh and S.Kumar, Applications of Arithmetic Operations in Digital Signal Processing: A Review. International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE), vol. 4, no. 6, pp. 1-7, June 2014.

[7]. A.Kaur and R.Mehra, Performance Analysis of Various Multipliers for Different Applications: A Review. International Journal of Engineering Research & Technology (IJERT), vol. 3, no. 11, pp. 1-5, November 2014.

[8]. S. K. Arun, B. Venkataramani, and M. Bhaskar. Analog Multiplier Design Using MOS Transistors. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 7, pp. 1009-1018, July 2000.

[9]. D. W. Matula. A Tutorial on Computer Arithmetic. IEEE Computer Society Press Tutorial Series, 1985, pp. 1-223.

[10]. S. Gunturi and V. G. Moshayedi.Design and Implementation of High Speed Multiplier Using Modified Booth Algorithm with Hybrid Carry Lookahead Adder. International Journal of Engineering Research & Technology (IJERT), vol. 2, no. 12, pp. 1-5, December 2013.

[11]. S. K. Singh, S. K. Singh, and A. K. Singh. A Fast Algorithm for Multidimensional Data Processing Using Wallace Trees. IEEE Transactions on Computers, vol. 66, no. 9, pp. 1628-1633, September 2017.

[12]. A. Nascimento and M. Vieira. A Survey on Multidimensional Data Structures for Spatial Queries. ACM Computing Surveys (CSUR), vol. 51, no. 2, pp. 1-36, April 2018.

[13]. S. Saha and S. Banerjee. A Comparative Study of Various Multiplier Architectures for High Speed Applications. International Journal of Engineering Research & Technology (IJERT), vol. 3, no. 10, pp. 1-6, October 2014.

[14]. S. S. Patil, S. S. Patil, and S. S. Patil. Design and Implementation of High Speed Multiplier Using Modified Booth Algorithm with Wallace Tree Reduction Technique. International Journal of Engineering Research & Technology (IJERT), vol. 6, no. 10, pp. 1-4, October 2017.

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