Approximation Design for Low Power Consumption in Digital Signal Processing Architecture: A Literature Review

Research Article
Open access

Approximation Design for Low Power Consumption in Digital Signal Processing Architecture: A Literature Review

Tianhong Zhong 1* , Songqi Shu 2 , Haoyuan Jing 3
  • 1 Montverde Academy Shanghai    
  • 2 Shanghai University    
  • 3 Yuming Senior high school    
  • *corresponding author ttz0319@hotmail.com
Published on 8 February 2025 | https://doi.org/10.54254/2755-2721/2024.20709
ACE Vol.132
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-941-0
ISBN (Online): 978-1-83558-942-7

Abstract

Given the power demands of DSP operations in portable or embedded devices, especially in error-resilient applications such as the multimedia and image processing, approximation strategy is proposed as a viable solution. By deliberately reducing computational precision, various DSP components —such as adders, multipliers, and compressors— can be designed with lower power requirements. This review explores the optimization of these components at different design levels, including architectural and circuit levels. Specifically, this paper goes deeper into the design of approximate adders, compressors, and multipliers, essentially highlighting their impact on power efficiency and computational accuracy for image/video compression applications. Through analyzing and discussing the different designs, this paper elaborates the trade-offs between power savings and error rates, ultimately demonstrating the potential of approximation techniques in reducing power consumption without significantly compromising performance.

Keywords:

Approximate Computing, Low Power Design, Digital Signal Processing, Multipliers and Compressors

Zhong,T.;Shu,S.;Jing,H. (2025). Approximation Design for Low Power Consumption in Digital Signal Processing Architecture: A Literature Review. Applied and Computational Engineering,132,225-240.
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References

[1]. Amir Momeni, Jie Han, Paolo Montuschi, and Fabrizio Lombardi. Design and analysis of approximate compressors for multiplication. IEEE Transactions on Computers, 64(4):984–994, 2014.

[2]. Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, and Kaushik Roy. Low-power digital signal processing using approximate adders. IEEE transactions on computer-aided design of integrated circuits and systems, 32(1):124–137, 2012.

[3]. Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. Dual-quality 4: 2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4):1352–1361, 2017.

[4]. Parag Kulkarni, Puneet Gupta, and Milos D Ercegovac. Trading accuracy for power in a multiplierˇ architecture. Journal of Low Power Electronics, 7(4):490–501, 2011.

[5]. Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, and Kaushik Roy. Impact: Imprecise adders for low-power approximate computing. In IEEE/ACM International Symposium on Low Power Electronics and Design, pages 409–414. IEEE, 2011.

[6]. Chip-Hong Chang, Jiangmin Gu, and Mingyan Zhang. Ultra low-voltage low-power cmos 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 51(10):1985–1997, 2004.

[7]. Eric J King and Earl E Swartzlander. Data-dependent truncation scheme for parallel multipliers. In Conference record of the thirty-first Asilomar conference on signals, systems and computers (Cat. No. 97CB36136), volume 2, pages 1178–1182. IEEE, 1997.

[8]. Jinghang Liang, Jie Han, and Fabrizio Lombardi. New metrics for the reliability of approximate and probabilistic adders. IEEE Transactions on computers, 62(9):1760–1771, 2012.

[9]. Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. Rap-cla: A reconfigurable approximate carry look-ahead adder. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(8):1089–1093, 2016.

Cite this article

Zhong,T.;Shu,S.;Jing,H. (2025). Approximation Design for Low Power Consumption in Digital Signal Processing Architecture: A Literature Review. Applied and Computational Engineering,132,225-240.

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About volume

Volume title: Proceedings of the 2nd International Conference on Machine Learning and Automation

ISBN：978-1-83558-941-0(Print) / 978-1-83558-942-7(Online)
Editor：Mustafa ISTANBULLU
Conference website: https://2024.confmla.org/
Conference date: 21 November 2024
Series: Applied and Computational Engineering
Volume number: Vol.132
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. Amir Momeni, Jie Han, Paolo Montuschi, and Fabrizio Lombardi. Design and analysis of approximate compressors for multiplication. IEEE Transactions on Computers, 64(4):984–994, 2014.

[2]. Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, and Kaushik Roy. Low-power digital signal processing using approximate adders. IEEE transactions on computer-aided design of integrated circuits and systems, 32(1):124–137, 2012.

[3]. Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. Dual-quality 4: 2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4):1352–1361, 2017.

[4]. Parag Kulkarni, Puneet Gupta, and Milos D Ercegovac. Trading accuracy for power in a multiplierˇ architecture. Journal of Low Power Electronics, 7(4):490–501, 2011.

[5]. Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, and Kaushik Roy. Impact: Imprecise adders for low-power approximate computing. In IEEE/ACM International Symposium on Low Power Electronics and Design, pages 409–414. IEEE, 2011.

[6]. Chip-Hong Chang, Jiangmin Gu, and Mingyan Zhang. Ultra low-voltage low-power cmos 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 51(10):1985–1997, 2004.

[7]. Eric J King and Earl E Swartzlander. Data-dependent truncation scheme for parallel multipliers. In Conference record of the thirty-first Asilomar conference on signals, systems and computers (Cat. No. 97CB36136), volume 2, pages 1178–1182. IEEE, 1997.

[8]. Jinghang Liang, Jie Han, and Fabrizio Lombardi. New metrics for the reliability of approximate and probabilistic adders. IEEE Transactions on computers, 62(9):1760–1771, 2012.

[9]. Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. Rap-cla: A reconfigurable approximate carry look-ahead adder. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(8):1089–1093, 2016.

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