Introduction and commercial prospect of GAAFET

Research Article
Open access

Introduction and commercial prospect of GAAFET

Yuchen Jiang 1*
  • 1 Viterbi School of Engineering, University of Southern California, Los Angeles, CA, 90089-0915, USA    
  • *corresponding author yjiang79@usc.edu
Published on 31 January 2024 | https://doi.org/10.54254/2755-2721/30/20230102
ACE Vol.30
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-285-5
ISBN (Online): 978-1-83558-286-2

Abstract

As recent metal-oxide-semiconductor field-effect transistor (MOSFET) technology developed, gate length shrinks so that engineers lost control of the transistor due to short channel effect and enormous leakage power. To maintain gate-to-channel control of the device, a fin field-effect transistor (FINFET) has been introduced to replace planar MOSFET technology. The "FIN" structure allows further down-scaling of gate length compared to planar MOSFET. As process node technology progresses, gate length scaling is stalled, where a further decrease of gate length would receive undesirable results in order of power, performance, and area (PPA). To escalate the transistor density, a new MOSFET design is required to replace FINFET. Therefore, the gate-all-around Multi-Bridge-Channel MOSFET (GAAFET or MBCFET) is successfully induced to be the feasible solution.

Keywords:

GAAFET, Gate-all-around, Nanowire, Nanosheet

Jiang,Y. (2024). Introduction and commercial prospect of GAAFET . Applied and Computational Engineering,30,224-229.
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References

[1]. Jurczak, M., Collaert, N., Veloso, A., Hoffmann, T., & Biesemans, S. (2009) Review of FINFET technology. 2009 IEEE International SOI Conference, Foster City, pp. 1-4.

[2]. Jang, D., Yakimets, D., Eneman, G., Schuddinck, P., Bardon, M. G., Raghavan, P., ... & Mocuta, A. (2017) Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node. IEEE Transactions on Electron Devices, vol. 64, no. 6, pp. 2707-2713.

[3]. Lee, H., Yu, L. E., Ryu, S. W., Han, J. W., Jeon, K., Jang, D. Y., ... & Choi, Y. K. (2006) Sub-5nm All-Around Gate FinFET for Ultimate Scaling. 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., Honolulu, pp. 58-59.

[4]. Das, U. K., & Bhattacharyya, T. K. (2020) Opportunities in Device Scaling for 3-nm Node and Beyond: FinFET Versus GAA-FET Versus UFET. IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2633-2638

[5]. Yoon, J. S., Jeong, J., Lee, S., Lee, J., & Baek, R. H. (2020) Gate-All-Around FETs: Nanowire and Nanosheet Structure. IntechOpen.

[6]. Loubet, N., Hook, T., Montanini, P., Yeung, C. W., Kanakasabapathy, S., Guillom, M., ... & Khare, M. (2017) Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symposium on VLSI Technology, Kyoto, pp. T230-T231.

[7]. Agha, F. N. H., Naif, Y. H., & Shakib, M. N. (2021). Review of nanosheet transistors technology. Tikrit Journal of Engineering Sciences, pp. 40-48.

[8]. Semiconductor Engineering. (2023) Gate-All-Around FET. https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/gate-all-around-fet/.

[9]. Lin, Y. W., Chang, H. H., Huang, Y. H., Sun, C. J., Yan, S. C., Lin, S. W., ... & Hou, F. J. (2021). Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance. IEEE Electron Device Letters, pp. 1727-1730

[10]. Lu, W., Xie, P., & Lieber, C. M. (2008). Nanowire transistor performance limits and applications. IEEE transactions on Electron Devices, pp. 2859-2876.

[11]. Knoedler, M., Bologna, N., Schmid, H., Borg, M., Moselund, K. E., Wirths, S., ... & Riel, H. (2017). Observation of twin-free GaAs nanowire growth using template-assisted selective epitaxy. Crystal Growth & Design, pp. 6297-6302.

[12]. Huang, Y. C., Chiang, M. H., Wang, S. J., & Fossum, J. G. (2017). GAAFET versus pragmatic FinFET at the 5nm Si-based CMOS technology node. IEEE Journal of the Electron Devices Society, pp. 164-169.

[13]. Samsung Semiconductor Global (2023) Samsung Opens the Gate to Transistor Performance, Power, and Area Improvements with MBCFET. semiconductor.samsung.com/newsroom/tech-blog/samsung-opens-the-gate-to-transistor-performance-power-and-area-improvements-with-mbcfet/.

[14]. Strategic Market Research. (2022) Gate-All-Around FET Technology Market 2021-2030. https://www.strategicmarketresearch.com/market-report/-gaafet-technology-market.

Cite this article

Jiang,Y. (2024). Introduction and commercial prospect of GAAFET . Applied and Computational Engineering,30,224-229.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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About volume

Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation

ISBN：978-1-83558-285-5(Print) / 978-1-83558-286-2(Online)
Editor：Mustafa İSTANBULLU
Conference website: https://2023.confmla.org/
Conference date: 18 October 2023
Series: Applied and Computational Engineering
Volume number: Vol.30
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. Jurczak, M., Collaert, N., Veloso, A., Hoffmann, T., & Biesemans, S. (2009) Review of FINFET technology. 2009 IEEE International SOI Conference, Foster City, pp. 1-4.

[2]. Jang, D., Yakimets, D., Eneman, G., Schuddinck, P., Bardon, M. G., Raghavan, P., ... & Mocuta, A. (2017) Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node. IEEE Transactions on Electron Devices, vol. 64, no. 6, pp. 2707-2713.

[3]. Lee, H., Yu, L. E., Ryu, S. W., Han, J. W., Jeon, K., Jang, D. Y., ... & Choi, Y. K. (2006) Sub-5nm All-Around Gate FinFET for Ultimate Scaling. 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., Honolulu, pp. 58-59.

[4]. Das, U. K., & Bhattacharyya, T. K. (2020) Opportunities in Device Scaling for 3-nm Node and Beyond: FinFET Versus GAA-FET Versus UFET. IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2633-2638

[5]. Yoon, J. S., Jeong, J., Lee, S., Lee, J., & Baek, R. H. (2020) Gate-All-Around FETs: Nanowire and Nanosheet Structure. IntechOpen.

[6]. Loubet, N., Hook, T., Montanini, P., Yeung, C. W., Kanakasabapathy, S., Guillom, M., ... & Khare, M. (2017) Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symposium on VLSI Technology, Kyoto, pp. T230-T231.

[7]. Agha, F. N. H., Naif, Y. H., & Shakib, M. N. (2021). Review of nanosheet transistors technology. Tikrit Journal of Engineering Sciences, pp. 40-48.

[8]. Semiconductor Engineering. (2023) Gate-All-Around FET. https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/gate-all-around-fet/.

[9]. Lin, Y. W., Chang, H. H., Huang, Y. H., Sun, C. J., Yan, S. C., Lin, S. W., ... & Hou, F. J. (2021). Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance. IEEE Electron Device Letters, pp. 1727-1730

[10]. Lu, W., Xie, P., & Lieber, C. M. (2008). Nanowire transistor performance limits and applications. IEEE transactions on Electron Devices, pp. 2859-2876.

[11]. Knoedler, M., Bologna, N., Schmid, H., Borg, M., Moselund, K. E., Wirths, S., ... & Riel, H. (2017). Observation of twin-free GaAs nanowire growth using template-assisted selective epitaxy. Crystal Growth & Design, pp. 6297-6302.

[12]. Huang, Y. C., Chiang, M. H., Wang, S. J., & Fossum, J. G. (2017). GAAFET versus pragmatic FinFET at the 5nm Si-based CMOS technology node. IEEE Journal of the Electron Devices Society, pp. 164-169.

[13]. Samsung Semiconductor Global (2023) Samsung Opens the Gate to Transistor Performance, Power, and Area Improvements with MBCFET. semiconductor.samsung.com/newsroom/tech-blog/samsung-opens-the-gate-to-transistor-performance-power-and-area-improvements-with-mbcfet/.

[14]. Strategic Market Research. (2022) Gate-All-Around FET Technology Market 2021-2030. https://www.strategicmarketresearch.com/market-report/-gaafet-technology-market.

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