Enhancing ASIC chip performance through integrated algorithm optimization

Research Article
Open access

Enhancing ASIC chip performance through integrated algorithm optimization

Shuying Xiao 1*
  • 1 Wuhan university of technology    
  • *corresponding author liuyunkai@whut.edu
Published on 7 February 2024 | https://doi.org/10.54254/2755-2721/38/20230563
ACE Vol.38
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-301-2
ISBN (Online): 978-1-83558-302-9

Abstract

As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achieving efficient parallel multiplication computations and reducing both latency and area complexity of multiplication. On the other hand, the Booth algorithm is an optimization method for signed binary multiplication. By introducing the concept of Booth encoding, it transforms signed multiplication into unsigned multiplication, thereby reducing the number of multiplication operations. This paper analyses the application and research progress of the Wallace Tree and Booth algorithms in the field of multiplier optimization to improve computational speed and reduce power consumption of multipliers.

Keywords:

Multiplier, Optimization, Wallace Tree, Booth Algorithm

Xiao,S. (2024). Enhancing ASIC chip performance through integrated algorithm optimization. Applied and Computational Engineering,38,274-279.
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References

[1]. Rene Davila Velarde,Ricardo Ramos Contreras,Luis Pizano Escalante,Omar Longoria Gandara & Cuauhtémoc Aguilera Galicia.(2023).Application-Specific Integrated Circuit of an Inter-IC Sound Digital Filter for Audio Systems. Applied Sciences(14).

[2]. Usenko E. A..(2022).Modern Application-Specific Integrated Circuits for Resistive Plate Chambers (Review). Instruments and Experimental Techniques(6).

[3]. Petrou Loukas,Kossifos Kypros M.,Antoniades Marco A. & Georgiou Julius.(2022).The first family of application-specific integrated circuits for programmable and reconfigurable metasurfaces. Scientific Reports(1).

[4]. Wang Li,Tao HuiBin,Dong Hang,Shao ZhiBiao & Wang Fei.(2020).A Non-Linear Temperature Compensation Model for Improving the Measurement Accuracy of an Inductive Proximity Sensor and Its Application-Specific Integrated Circuit Implementation. Sensors(17).

[5]. Bahram Rashidi.(2019).Efficient and high-throughput application-specific integrated circuit implementations of HIGHT and PRESENT block ciphers. IET Circuits, Devices & Systems(6).

[6]. N. Arumugam & B. Paramasivan.(2021).An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction of noise in the sensor nodes. Multidimensional Systems and Signal Processing(4).

[7]. M. Arulkumar & M. Chandrasekaran.(2021).An Improved VLSI Design of the ALU Based FIR Filter for Biomedical Image Filtering Application. Current Medical Imaging(2).

[8]. John Mar M. Castillo, Sarah Mae B. Macabangon, Ricardo Gary B. Garcia III... & Michael John M.Villar.(2019).Construction of Carbon Fiber Industry Chain Integration Framework Based on Industrial Technology Breakthrough. Indian Journal of Public Health Research & Development(1).

[9]. Lakshmi kiranMukkara & Kota VenkataRamanaiah.(2018).FPGA Implementation of High Speed Digital FIR Filter. International Journal of Advanced Networking and Applications(2).

[10]. Pratibhadevi Tapashetti, Dr. Rajkumar B Kulkarni & Dr.S S Patil.(2016).Research on the “Last Kilometer” Distribution Model of Cold Chain Logistics. Indian Journal of Public Health Research & Development(12).

[11]. Pouya Asadi.(2016).A New Array Multiplier Using an Optimized Carry Network and Dynamic CMOS Technology. Journal of Circuits, Systems and Computers(2).

[12]. Xiang Ping Qian,Wei Ming Qiao,Zhong Zu Zhou... & Lan Jing.(2012).A Digital Regulator for FPGA Implementation. Advanced Materials Research(433-440).

[13]. P. Saha,A. Banerjee,A. Dandapat & P. Bhattacharyya.(2011).Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors. International Journal on Smart Sensing and Intelligent Systems(2).

[14]. Sharmila Hemanandh & Siva Subramanium.(2015).Performance Evaluation of High Speed Radix 8 Tree Based Multiplier. Indian Journal of Science and Technology(33).

[15]. Pouya Asadi.(2015).A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network. International Journal of Information Engineering and Electronic Business(IJIEEB)(4).

[16]. Himanshu Bansal,K. G. Sharma & Tripti Sharma.(2014).Wallace Tree Multiplier Designs: A Performance Comparison Review. Innovative Systems Design and Engineering.

Cite this article

Xiao,S. (2024). Enhancing ASIC chip performance through integrated algorithm optimization. Applied and Computational Engineering,38,274-279.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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About volume

Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation

ISBN：978-1-83558-301-2(Print) / 978-1-83558-302-9(Online)
Editor：Mustafa İSTANBULLU
Conference website: https://2023.confmla.org/
Conference date: 18 October 2023
Series: Applied and Computational Engineering
Volume number: Vol.38
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. Rene Davila Velarde,Ricardo Ramos Contreras,Luis Pizano Escalante,Omar Longoria Gandara & Cuauhtémoc Aguilera Galicia.(2023).Application-Specific Integrated Circuit of an Inter-IC Sound Digital Filter for Audio Systems. Applied Sciences(14).

[2]. Usenko E. A..(2022).Modern Application-Specific Integrated Circuits for Resistive Plate Chambers (Review). Instruments and Experimental Techniques(6).

[3]. Petrou Loukas,Kossifos Kypros M.,Antoniades Marco A. & Georgiou Julius.(2022).The first family of application-specific integrated circuits for programmable and reconfigurable metasurfaces. Scientific Reports(1).

[4]. Wang Li,Tao HuiBin,Dong Hang,Shao ZhiBiao & Wang Fei.(2020).A Non-Linear Temperature Compensation Model for Improving the Measurement Accuracy of an Inductive Proximity Sensor and Its Application-Specific Integrated Circuit Implementation. Sensors(17).

[5]. Bahram Rashidi.(2019).Efficient and high-throughput application-specific integrated circuit implementations of HIGHT and PRESENT block ciphers. IET Circuits, Devices & Systems(6).

[6]. N. Arumugam & B. Paramasivan.(2021).An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction of noise in the sensor nodes. Multidimensional Systems and Signal Processing(4).

[7]. M. Arulkumar & M. Chandrasekaran.(2021).An Improved VLSI Design of the ALU Based FIR Filter for Biomedical Image Filtering Application. Current Medical Imaging(2).

[8]. John Mar M. Castillo, Sarah Mae B. Macabangon, Ricardo Gary B. Garcia III... & Michael John M.Villar.(2019).Construction of Carbon Fiber Industry Chain Integration Framework Based on Industrial Technology Breakthrough. Indian Journal of Public Health Research & Development(1).

[9]. Lakshmi kiranMukkara & Kota VenkataRamanaiah.(2018).FPGA Implementation of High Speed Digital FIR Filter. International Journal of Advanced Networking and Applications(2).

[10]. Pratibhadevi Tapashetti, Dr. Rajkumar B Kulkarni & Dr.S S Patil.(2016).Research on the “Last Kilometer” Distribution Model of Cold Chain Logistics. Indian Journal of Public Health Research & Development(12).

[11]. Pouya Asadi.(2016).A New Array Multiplier Using an Optimized Carry Network and Dynamic CMOS Technology. Journal of Circuits, Systems and Computers(2).

[12]. Xiang Ping Qian,Wei Ming Qiao,Zhong Zu Zhou... & Lan Jing.(2012).A Digital Regulator for FPGA Implementation. Advanced Materials Research(433-440).

[13]. P. Saha,A. Banerjee,A. Dandapat & P. Bhattacharyya.(2011).Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors. International Journal on Smart Sensing and Intelligent Systems(2).

[14]. Sharmila Hemanandh & Siva Subramanium.(2015).Performance Evaluation of High Speed Radix 8 Tree Based Multiplier. Indian Journal of Science and Technology(33).

[15]. Pouya Asadi.(2015).A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network. International Journal of Information Engineering and Electronic Business(IJIEEB)(4).

[16]. Himanshu Bansal,K. G. Sharma & Tripti Sharma.(2014).Wallace Tree Multiplier Designs: A Performance Comparison Review. Innovative Systems Design and Engineering.

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