1. Introduction

In VLSI design, the key problems in SRAM design include the stability, read, and write delay, power consumption and reliability of the memory cell. SRAM design is an important research direction in VLSI field, involving circuit design, process design, layout design, timing analysis and optimization [1]. Combined with authoritative academic articles in VLSI, SRAM and machine learning related fields, this article mainly discusses the application of machine learning in SRAM circuit design.

The article mentions several aspects of application analysis, including: Firstly, SRAM design for machine learning applications, aiming to provide high energy efficiency and high bandwidth memory solutions. Secondly, SRAM PUF design for machine learning modeling attacks, with good attack resistance. Thirdly, a lightweight fault-tolerant mechanism is proposed. Fourthly, apply reinforcement learning and Markov decision process (MDP) to realize the interconnection resource allocation of SRAM FPGAs [2]. Finally, the application of machine learning in SRAM power optimization and privacy security is discussed. The significance of machine learning in VLSI applications is to provide an intelligent method and tool that can speed up the design process, improve system performance, increase reliability, and drive the advancement of chip manufacturing and processes.

2. The theoretical foundation of machine learning and SRAM

2.1. SRAM

SRAM is a common computer memory technology with theoretical foundations in semiconductor physics, circuit design and digital logic. SRAM uses trigger circuits to store and read data, and is often used for applications that require fast access, such as caches and register files. The basic memory unit structure of the SRAM is a flip-flop circuit, usually composed of six transistors [3]. This circuit can store a bit (0 or 1) and read and write data through the control input and read and write lines. The memory unit of the SRAM performs write and read operations by controlling the input signal. The write operation writes data to the storage unit, while the read operation obtains data from the storage unit. These operations involve the control and drive of components such as bit line, word line and transfer gate. The graph of serial SARM is shown in figure 1.

Figure 1. Graph of serial SARM (Photo/Picture credit: Original).

It usually organizes storage units in the form of arrays, where each storage unit has a unique address [4]. The address line is used to select a specific storage unit to be read or written to, so that access to the memory can be completed in a constant time. The read operation of the SRAM involves sensing and amplifying the storage unit to ensure that the stored data is read correctly [5]. The write operation requires making changes to the charge of the storage cell and ensuring that the data is written correctly. It requires a proper power supply and has a stable voltage and signal amplitude to ensure correct storage and read operation.

2.2. Machine Learning

The theoretical foundations of machine learning include statistics, probability theory, linear algebra, and optimization theory. It involves algorithms and methods for learning patterns and patterns from data. In machine learning, SRAM can be used as a hardware accelerator to store and manipulate model parameters or intermediate results, thereby increasing computational efficiency and throughput [6]. Combining machine learning algorithms with SRAM enables a faster model inference and training process. Machine learning processes large data sets to make predictions or decisions based on patterns and patterns in the extracted data. Machine learning can be applied to many aspects of SRAM design, such as layout and routing, fault detection, fault tolerant design, and power optimization.

3. Application analysis of machine learning in SRAM circuit design

3.1. Line routing and timing analysis

In order to address the challenge of applying machine learning to SRAM circuit wiring, Sung Kyu Lim propose that the newest ICs technology could overcome the limitations of integrating 2D/3D circuits. The 3D IC technology could be used to combine various devices like CMOS, RRAM and SRAM within a single chip [7]. Including the generation of technology files, the use of pseudo3D flows for standard cell designs, and the use of macro-on-logic (MoL) flows for designs with hard macros. Heterogeneous 3D ICs will help improve timing and power performance, signal and power integrity, and explore potential integration techniques in the future.

Mingn Kang and Naresh R. Shanbhag proposed to implement (RF) machine learning classifiers using in-memory computing methods. The main innovation of their proposed method lies in the use of DSS and balanced decision trees [8]. Through their prototype IC implementation, they achieve a remarkable energy savings of 3.1 times compared to conventional digital architecture along with a speed-up factor of 2.2 times. This results in a significantly lower energy-delay product (EDP) by approximately 6.8 times at an accuracy level exceeding 93%. These techniques effectively contribute towards achieving energy savings, reduced decision delay, and improved energy efficiency when compared to traditional digital architectures.

3.2. SRAM testing and fault diagnosis

Memory-based Physical Unclonable Functions (PUFs), such as SRAM PUFs, are highly attractive due to their extensive usage in embedded systems and minimal additional hardware requirements. SRAM PUFs utilize the initial values of SRAM memory cells as a unique digital fingerprint. Our objective is to enable authentication of devices even in the presence of data loss caused by transmission errors, without relying on complex error-correcting techniques. Nico Mexis think Convolutional Neural Networks (CNN) can be employed for classifying and identifying SRAM PUF responses [9]. To address challenges related to noisy datasets and data corruption, researchers manually manipulated the data by converting a portion of the response data into zero values, simulating data corruption. These data were then transformed into binary arrays and grayscale images before being classified and identified using a CNN model. The proposed approach achieves an accuracy rate of 96.85% for intact images and 95.46% for noisy images. Furthermore, it demonstrates accurate classification capabilities even with up to a 30% loss in data integrity. However, when the corruption rate exceeds 30%, the performance of the model starts deteriorating significantly. By utilizing a combined dataset during training, we can enhance the classification performance for both corrupted and intact images; however, accurately classifying images with 40% corruption remains challenging using our current model configuration. Overall, this method presents a novel approach towards authenticating SRAM PUFs while partially addressing concerns associated with data corruption.

There are certain challenges, such as the NP-complete problem, that make it quite challenging to find the best solution. The utilization of reinforcement learning in testing and diagnosing. In an article, Aokai Shi discusses how RL-based MDP is employed to implement interconnect resource configurations for SRAM FPGAs [9]. By utilizing dynamic programming, the authors successfully solve the MDP and achieve comprehensive coverage of interconnect resources. This innovative approach optimizes configuration numbers and addresses the challenge of achieving full coverage in NP-complete problems like FPGA testing. Experimental results demonstrate that this method effectively optimizes configuration numbers towards a theoretical value while ensuring complete coverage, making it applicable to NP-complete issues encountered during FPGA testing.

3.3. Fault recovery and fault tolerance

AnQi Zhang proposes the utilization of CNT SRAM memory [10]. Modifications are made to the NeuroSim tool to analyze how different fault patterns affect the memory units after recovering from stuck-at faults. The paper also presents mechanisms for fault recovery that aim to improve system accuracy. By leveraging emerging technology like CNT SRAM, it becomes possible to effectively address high fault rates and enhance overall system accuracy. The study examines various fault patterns and locations while offering techniques for optimizing system accuracy. Despite the availability of open-source NVDLA and ONNC, challenges still exist during the mass production stage of AI chip development, such as issues with SRAM MBIST fail and scan-chain fail leading to reduced productivity.

To tackle internal SRAM stuck faults, Luba Tang proposes a lightweight fault-tolerance mechanism [11]. By employing ONNC, the authors suggest employing lightweight recovery mechanisms like adjacent bit mechanism and barrel shift to address input faults. Additionally, they explore SRAM Analyzer for reconfiguring and integrating these fault recovery mechanisms into the SRAM compiler to ensure usage in CNN [12]. Experimental results demonstrate that this method can optimize configuration numbers towards achieving theoretical coverage with full effectiveness, making it suitable for NP-complete problems such as FPGA testing.

3.4. SRAM power optimization and privacy security

The major portion of power dissipation in deep learning networks is attributed to the read operations involved in fetching network weights. Saranyu Chattopadhyay and Kaustav Brahma think STT-MRAM can optimize power consumption. Voltage-mode sensing can achieve a high level of Tunnel Magnetoresistance (TMR) by utilizing a read operation with lower voltage and thicker oxide. The combination of reduced voltage during read operations and increased thickness of the oxide layer contributes to the achievement of higher TMR in voltage-mode sensing. Firstly, it allows for more aggressive scaling down and causes the energy consumption decreased. What’s more, there is no static current path which could lead further reduction in power usage [13].

To address the vulnerability of PUF-based protocols to modeling attacks, Jimson Mathew proposes a SRAM PUF that exhibits strong resistance against such attacks. Their main research approach involves designing and implementing the 2SPUF architecture, which is a Two Round SRAM PUF [14]. A key innovation presented in this paper is the introduction of a two-round SRAM PUF architecture called 2SPUF that effectively mitigates machine learning modeling attacks. This unique feature enhances the resilience of the 2SPUF architecture against modeling attacks while experimental results validate its effectiveness in resisting such attacks by demonstrating improved accuracy.

4. Conclusion

This paper combined with authoritative academic articles in VLSI, SRAM and machine learning related fields to analyze the specific application examples of machine learning in SRAM circuit design. For Optimized design, machine learning can be applied to circuit and chip design processes to automatically discover and optimize circuit structure, layout, and characteristics by analyzing large amounts of data and patterns. This can improve circuit performance, power consumption and reliability. For Fault detection and fault tolerance, machine learning can be used to develop fault detection algorithms and fault tolerance mechanisms to improve system reliability and stability. For Testing and verification, machine learning can identify potential errors, vulnerabilities, and anomalies to provide a more comprehensive and efficient approach to testing and verification by learning from large test samples and historical data, machine learning algorithms. For Error correction and repair, machine learning can automatically correct and repair errors by learning known error patterns and solutions. This saves time and labor costs and improves the maintainability of the system.

Machine learning has a broad application prospect in SRAM design. Firstly, by using machine learning, SRAM performance can be modeled and optimized. Machine learning algorithms can analyze large amounts of SRAM performance data and discover the effects of different design parameters on performance to guide the design process. Secondly, Machine learning can identify patterns and related factors that cause failures by analyzing large-scale reliability data. This can help designers take appropriate measures to improve SRAM reliability. Thirdly, Machine learning can help designers find the best power optimization strategy by learning and predicting the relationship between different design parameters and power consumption. This approach can reduce the contribution of SRAM to the overall chip power consumption, thereby extending the chip’s battery life or reducing heat dissipation requirements. It is important to note that the application of machine learning in SRAM design is still in the stage of continuous development and exploration. As the technology advances and more research is carried out, it can expect to see more innovative applications of machine learning in SRAM design.