References
[1]. Suri, L. , Lamba, D. , Kritarth, K. , & Sharma, G. (2013). High performance and power efficient 32-bit carry select adder using hybrid PTL/CMOS logic style. International Multi-conference on Automation. IEEE.
[2]. Sharma, G. , Nirmal, U. , & Misra, Y. (2011). A Low Power 8-bit Magnitude Comparator with Small Transistor Count using Hybrid PTL/CMOS Logic.
[3]. Luan, Lili. (2017). Characterization and comparison of single-supply absolute value circuits. Electronic Fabrication (22), 2.
[4]. Li, Y.-J., Wu, Y.-W., Zhang, E.-S., & Liang, Y. (2017). Front-end sampling design of active power filter based on absolute value circuit. Yunnan Power Technology (Vol. 45, pp. 3).
[5]. Iranmanesh, S. , Raikos, G. , Jiang, Z. , & Rodriguez-Villegas, E. (2016). CMOS implementation of a low power absolute value comparator circuit. New Circuits & Systems Conference. IEEE.
[6]. Kumngern, M. (2013). Absolute Value Circuit for Biological Signal Processing Applications. Proceedings of the 2013 4th International Conference on Intelligent Systems, Modelling and Simulation. IEEE.
[7]. Wu, Jian, Wu, W., & Jia, Qianwei. (2012). Application of absolute value circuits in analog-to-digital conversion. Automation Technology and Applications (8), 3.
[8]. Bhuyan, Muhibul & Riyadh, Md. Mubarak & Hossain, Md & Rahman, Md. (2020). Design and Simulation of a Low Design and Simulation of a Low Power and High-Speed 4-Bit Magnitude Comparator Circuit using CMOS in DSch and Microwind. 20. 82-94.
[9]. Mukherjee, D. N. , Panda, S. , & Maji, B. (2017). Design of Low Power 12-bit Magnitude Comparator. International Conference on Devices for Integrated Circuit.
[10]. Weste, N. , & Eshraghian, K. (1993). Principles of CMOS VLSI Design: Second Edition.
[11]. Chandrakasan, A. , & Brodersen, R. Low-Power CMOS Design. IEEE Xplore.
[12]. Morgenshtein, A. , Fish, A. , & Wagner, I. A. (2002). Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Educational Activities Department.
Cite this article
Wang,Y. (2024). Design and analysis of 4-bit absolute-value comparator in 65nm technology using hybrid TG/CMOS. Applied and Computational Engineering,39,189-200.
Data availability
The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.
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References
[1]. Suri, L. , Lamba, D. , Kritarth, K. , & Sharma, G. (2013). High performance and power efficient 32-bit carry select adder using hybrid PTL/CMOS logic style. International Multi-conference on Automation. IEEE.
[2]. Sharma, G. , Nirmal, U. , & Misra, Y. (2011). A Low Power 8-bit Magnitude Comparator with Small Transistor Count using Hybrid PTL/CMOS Logic.
[3]. Luan, Lili. (2017). Characterization and comparison of single-supply absolute value circuits. Electronic Fabrication (22), 2.
[4]. Li, Y.-J., Wu, Y.-W., Zhang, E.-S., & Liang, Y. (2017). Front-end sampling design of active power filter based on absolute value circuit. Yunnan Power Technology (Vol. 45, pp. 3).
[5]. Iranmanesh, S. , Raikos, G. , Jiang, Z. , & Rodriguez-Villegas, E. (2016). CMOS implementation of a low power absolute value comparator circuit. New Circuits & Systems Conference. IEEE.
[6]. Kumngern, M. (2013). Absolute Value Circuit for Biological Signal Processing Applications. Proceedings of the 2013 4th International Conference on Intelligent Systems, Modelling and Simulation. IEEE.
[7]. Wu, Jian, Wu, W., & Jia, Qianwei. (2012). Application of absolute value circuits in analog-to-digital conversion. Automation Technology and Applications (8), 3.
[8]. Bhuyan, Muhibul & Riyadh, Md. Mubarak & Hossain, Md & Rahman, Md. (2020). Design and Simulation of a Low Design and Simulation of a Low Power and High-Speed 4-Bit Magnitude Comparator Circuit using CMOS in DSch and Microwind. 20. 82-94.
[9]. Mukherjee, D. N. , Panda, S. , & Maji, B. (2017). Design of Low Power 12-bit Magnitude Comparator. International Conference on Devices for Integrated Circuit.
[10]. Weste, N. , & Eshraghian, K. (1993). Principles of CMOS VLSI Design: Second Edition.
[11]. Chandrakasan, A. , & Brodersen, R. Low-Power CMOS Design. IEEE Xplore.
[12]. Morgenshtein, A. , Fish, A. , & Wagner, I. A. (2002). Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Educational Activities Department.