Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

Research Article
Open access

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

Fuchang Wen 1*
  • 1 Northeastern University at Qinhuangdao    
  • *corresponding author 202012725@stu.neu.edu.cn
Published on 21 February 2024 | https://doi.org/10.54254/2755-2721/39/20230604
ACE Vol.39
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-303-6
ISBN (Online): 978-1-83558-304-3

Abstract

To deeply understanding of brain function, the rapid and accurate extracting relevant signals during brain operation has become increasingly important. As our understanding of brain function advances, the ability to extract relevant signals quickly and accurately becomes increasingly crucial. Therefore, a 16-bit spike detector has been designed to detect neural signals. Since a 4-bit absolute value detector is a critical module of the 16-bit spike detector, this paper presents a design for a 4-bit value comparator using a chain adder and a comparator. Two methods, changing the supply voltage and changing the gate size, were utilized to reduce power consumption, and it was found that changing the supply voltage method was more effective. Additionally, the circuit’s layout was designed for simulation to enhance the authenticity and reliability of the results. Currently, brain-computer interface technology remains a widely discussed topic in the field of neuroscience, and the speed and accuracy of neural signal processing continue to be critical issues that need to be addressed.

Keywords:

4-bit Absolute Value Comparator, BCI Technology, Optimization, Layout

Wen,F. (2024). Design and optimization of a 16-bit spike detector based on 90nm CMOS technology. Applied and Computational Engineering,39,230-243.
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References

[1]. Lewicki M S. A review of methods for spike sorting: the detection and classification of neural action potentials. Network, 1998.

[2]. Obeid I, Wolf P D. Evaluation of spike-detection algorithms for a brain-machine interface application. Biomedical Engineering IEEE Transactions on, 2004, 51(6):905-911.

[3]. Noninvasive Brain–Machine Interfaces for Robotic Devices. Annual Review of Control Robotics and Autonomous Systems, 2021, 4(1).

[4]. D Valencia, Alimohammad A. Neural Spike Sorting Using Binarized Neural Networks. IEEE Transactions on Neural Systems and Rehabilitation Engineering, 2020, (99):1-1.

[5]. Yuan, M. An absolute-value detector with threshold comparing for spike detection in the brain-machine interface. Journal of Physics: Conference Series, 2021, 2113(1): 012038.

[6]. Charles S. De Morgan’s law and theorems. 2013.

[7]. S. Prema. Comparative Analysis of Different Full Adder Circuits. Programmable Device Circuits and Systems,2013,5(2).

[8]. Efstathiou Constantinos,Kitsos Paris. Efficient majority logic magnitude comparator design. Microprocessors and Microsystems,2021,82.

[9]. Efstathiou, C., & Kitsos, P . Efficient majority logic magnitude comparator design. Microprocessors and Microsystems, 2021, 82: 103-112.

[10]. Sharroush, S. M., & Abdalla, Y. S. Parameter extraction and modelling of the MOS transistor by an equivalent resistance. Mathematical and Computer Modeling of Dynamical Systems, 2021, 27(1): 50–86.

[11]. Kim, K., & Park, S. Delay-time modeling and critical-path verification for CMOS digital designs. Computer-Aided Design, 1991, 23(9): 604–614.

[12]. Sharma, V., & Rajawat, A. Review of Approaches for Radiation Hardened Combinational Logic in CMOS Silicon Technology. IETE Technical Review, 2018, 35(6): 562–573.

Cite this article

Wen,F. (2024). Design and optimization of a 16-bit spike detector based on 90nm CMOS technology. Applied and Computational Engineering,39,230-243.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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About volume

Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation

ISBN：978-1-83558-303-6(Print) / 978-1-83558-304-3(Online)
Editor：Mustafa İSTANBULLU
Conference website: https://2023.confmla.org/
Conference date: 18 October 2023
Series: Applied and Computational Engineering
Volume number: Vol.39
ISSN：2755-2721(Print) / 2755-273X(Online)

© 2024 by the author(s). Licensee EWA Publishing, Oxford, UK. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license. Authors who publish this series agree to the following terms:
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References

[1]. Lewicki M S. A review of methods for spike sorting: the detection and classification of neural action potentials. Network, 1998.

[2]. Obeid I, Wolf P D. Evaluation of spike-detection algorithms for a brain-machine interface application. Biomedical Engineering IEEE Transactions on, 2004, 51(6):905-911.

[3]. Noninvasive Brain–Machine Interfaces for Robotic Devices. Annual Review of Control Robotics and Autonomous Systems, 2021, 4(1).

[4]. D Valencia, Alimohammad A. Neural Spike Sorting Using Binarized Neural Networks. IEEE Transactions on Neural Systems and Rehabilitation Engineering, 2020, (99):1-1.

[5]. Yuan, M. An absolute-value detector with threshold comparing for spike detection in the brain-machine interface. Journal of Physics: Conference Series, 2021, 2113(1): 012038.

[6]. Charles S. De Morgan’s law and theorems. 2013.

[7]. S. Prema. Comparative Analysis of Different Full Adder Circuits. Programmable Device Circuits and Systems,2013,5(2).

[8]. Efstathiou Constantinos,Kitsos Paris. Efficient majority logic magnitude comparator design. Microprocessors and Microsystems,2021,82.

[9]. Efstathiou, C., & Kitsos, P . Efficient majority logic magnitude comparator design. Microprocessors and Microsystems, 2021, 82: 103-112.

[10]. Sharroush, S. M., & Abdalla, Y. S. Parameter extraction and modelling of the MOS transistor by an equivalent resistance. Mathematical and Computer Modeling of Dynamical Systems, 2021, 27(1): 50–86.

[11]. Kim, K., & Park, S. Delay-time modeling and critical-path verification for CMOS digital designs. Computer-Aided Design, 1991, 23(9): 604–614.

[12]. Sharma, V., & Rajawat, A. Review of Approaches for Radiation Hardened Combinational Logic in CMOS Silicon Technology. IETE Technical Review, 2018, 35(6): 562–573.

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