1. Introduction
Mosfet, as the basic part of modern integrated circuit, works in various situation, with different working states required. As the specific circumstances would have their own expectations about the functions of mosfets, mosfets also varies the design to suit the expectation. There become mosfets of different materials, like SiC mosfet for drive circuit, GaN mosfet for high power device, and mosfets of different constructure, like SGT mosfet for circuits of low voltage, SG mosfet for circuits of high voltage. However, being sensitive with external parameters, the entire integrated circuit would come to failure with the mosfets working in the wrong state, or losing the function required. Since the mosfets varies in circuits, the failure modes of each mosfet also varies, which means that the circuits would have different improvements to deal with the failure mode.
This article would make some basic classifications on the failure mode of mosfets, introduce the principle of it and the methods proposed by former studies on each situation.
The first chapter is the introduction, introducing the background and the research significance. The second chapter would give out the classifications of failure modes with examples of each mode. With the classifications given above, the third chapter would summarize some methods of solutions on the failure modes above. The fourth chapter would be the summary, summarizing the entire article and giving out the reflection.
2. Failure Modes
Basically, the failure mode of mosfet could be divided into 4 sorts: the failure caused by the constructure of the mosfet itself; the failure of extreme environment; the failure of the combine action; and the failure of manufacturing technique. The boundary between each two sorts is not separated apart clearly, for these modes could happen together in a function close to chain reaction, leading and strengthening each other with their effects.
There have been various methods to evaluate the failure mode, developed by different government or industry entities, with different effects of the material. With the designed experiments, as the experiments of evaluating GaN material moffets, some parameters given by the experiment of the mosfet would be detected, as the sign of the failure state, showing out the image connection between the related parameters of exact changing states, recording how the mosfets come to failure mode with external situations. [1,2]
2.1. The Failure of Mosfet Constructure
Origin mosfets is a simple device with a small range of working parameters, which works only as switch driven by voltage with also a small range. Mostly, this basic constructure would work in simple logic circuit, which requires no harsh working situations and exceptions about the value of the parameters of the working states. If the circuit works in other states or requires the mosfet to play other roles, the mosfet needs to change its own construction to suit the new environment and the circuit parameters.
In order to meet the requirements of mosfets, the basic construction of mosfets would change to get better performance in circuit. These changes not only lead to the improvement of circuit performance, but also the electrical characteristic with different constructures. Take an example: as SiC mosfets, to suit the requirements of lower resistance and the ability of high voltage resistance, would use the material of SiC, the material of wider bandgap. As the material not only influences the resistance and the voltage available, in order to get a proper value of the threshold voltage with wider bandgap, the oxide layer is supposed to be thinner, which not only leads to a shorter lifetime, but also decrease the difference between the oxide layer and these two substrates, making the tunnel effect more likely to happen, breaking the oxide layer at the same time. Also, SiC as a solid material of higher Young's modulus, has to face the issue of aging with the thermal stress effect.
In this case, the improvement in constructure leads to further issues with the electronical characteristic changed by it. The device has to retire more quickly and to work in a stricter environment to protect the oxide layer on the gate [3,4].
2.2. The Failure of Extreme Environment
Mostly, the mosfets wouldn’t work in extreme environments, but taking the same duty in a stable environment all the time. Though, this kind of failure also happens, behind the normal value of the parameters, with the factors of failure increases with time naturally, collecting quite large amount of abnormal values of parameters which were supposed to remain a stable standard. Also, in some cases, the working state of the mosfets would change, such as working as a switch, requiring the parameters moves quickly in a large range, which will also cause an extreme environment.
All the mosfets works with the insulated isolation, as the method to add a external control to the circuit without disturbing the circuit, by which way the circuit is able to decide which path to be conducted and which path to be blocked. However, the insulated isolation only works with proper conditions. Take power mosfet, which is of high resistance and low capacitance, quite easy to hold a high voltage, as an example. With such resistance and capacitance, power mosfet would easily collects a large value of voltage with quite little charge, breaking the insulated isolation built by oxide layer, ruin the function of external control to the circuit. Rather than such result of accumulation, there would also be sudden and instantaneous extreme environments, with some mutations of the circuit as the circuit being short circuited.
Also, there is another path to the extreme environment, weaking the materials in which way the normal condition before would be the condition of extreme environment now. The devices never work in ideal environments, the working situation would always cause damage to the devices, which will weak the strength, leading to aging effects. As all the materials are aging, being more fragile with external circumstance, the ability to remain a stable function would decrease, making the device tend to fail with normal working states. [5,6].
2.3. The Failure of Manufacturing Technique
In the manufacturing procession, even mistakes quite little would cause the circuit to suffer from great load which will disturb the circuit from normal working state and even stability in physics, decrease the lifetime and influence the function of the circuit negatively both in mechanics and electricity. The mismatch in the bonding would lead to extra force, letting the different parts between the mistake parts always holding a load of it. The materials would both get tired and create extra current with the circuit built by the mismatched path, decreasing the performance in heat dissipation and electric conduction, increasing the danger of overheat and other electric failure.
This kind of failure mode could also be divided into two different types. The first type is the inevitable failure. In some manufacturing processions, due to the nature drawbacks of the materials, the manufacture would always face the flaws which may lead to failure of the device. SiC mosfets could be an example of this case. As the Carbon on the interface always becomes clusters or concentrate in one zone, the interface would be extremely rough with traps and flaws. With these unpredictable and various drawbacks, the parameters of the device won’t be stable. These traps and flaws will even grow inside the devices, decreasing the age and the reliability [3].
The second type is the evitable drawbacks, which are able to be controlled by controlling the procession of the manufacture. In this case, the devices simply show different features in different environment of manufacture. As existing research shows, thermal oxidation would lead to charges with negative electricity in the oxide layout of gate, disturbing the normal curve of working state of mosfets. However, with different annealing processions, the disturbance also varies with the changes of the manufacture, which makes this phenomenon controllable with the controllable manufacture [7].
3. The Method of Improvement
As modern integrated circuit works with great numbers of devices, a normal waking state would require a high rate of devices working regularly. In which way, most failure modes are supposed to be weaken. Aim at the failure modes above, this chapter would summarize some methods of improvement proposed by existing researches on each mode.
3.1. Improvements on the Failure of Mosfet Constructure
Based on the requirements of the devices, the constructure of devices cannot be changed, which means that the drawbacks of that constructure also remains, with the shortcomings of the materials. There would be two methods in normalizing the usage of these devices, to get to know about the specific mathematic model how the devices work, making the devices only work in a proper state which is stable and continuous for them, and to improve the materials themselves, so that the devices would get a better performance in the circuit.
Also taking Sic mosfets as an example, the prior research would concentrate on analysing many specific fields of the electric functions of the materials and how the devices respond to external parameters, with many given parameters of the traps and flaws which will show the actions of the devices. With the tunnel effect mentioned above, there are models to describe the effect of this failure mode mathematically.
As there are thermionic emission mode:
\( J=C{E_{ox}}[\frac{-q(Φ-\sqrt[]{\frac{q{E_{ox}}}{π{ε_{r}}}})}{α kt}] \) (1)
Phonon-assisted tunneling mode:
\( {W_{mp}}∝S|V{|^{2}}{(1-\frac{l}{s})^{2}}\frac{1}{ћω}{({l^{2}}+{ξ^{2}})^{\frac{1}{4}}}{(\frac{ξ}{l+{({l^{2}}+{ξ^{2}})^{\frac{1}{2}}}})^{l({({l^{2}}+{ξ^{2}})^{\frac{1}{2}}}-({f_{B}}+1)S+\frac{∆E}{2kT})}} \) (2)
Et cetera [8].
Material improvement is also happening along with the integrated circuit. Different manufactures in producing SiC material have been improved to deal with the nature drawbacks of these devices. Also, there would be replacing materials, as SoC for SiC, which shows better performance in gate oxide breakdown effect. [8,9]
3.2. Improvements on the Failure of Extreme Environment
This kind of failure is mostly caused by the accumulation of some factors, or mutations sudden and instantaneous. The solution should be based on two accesses: to make the devices able to bear the extreme environment, or to avoid the environment appearing in the circuit.
The simplest way should be choosing the devices of larger limit parameters, with enough margin left for the extreme situations. However, as the limit parameters won’t be too large due to the limitations of the materials and constructures of the devices, this method won’t be a universal solution, for it can’t deal with external parameters extreme enough, also influencing the electrical characteristics of the entire circuit, with the devices not being expected originally.
A more promising method should be adding a protecting circuit externally, which would only work when extreme environment happens, sharing the dangerous value of parameters which may lead the devices to failure, helping them always work in a safe state, both for the circuit requirements and the devices. With the same principle, there are also methods for external parameters of no electrical characteristics like temperature, pressure, humidity…By adding passivation layer on the devices, insulating the unexpected extreme environment outside the working area. What is supposed to be noticed is that both protecting circuit and passivation layer would also change the characteristics of the circuit and the devices, there still requires examination on whether the circuit or the devices meet the original expectation with such improvements [5, 10].
3.3. Improvements on the Failure of Manufacturing Technique
Failure mode of manufacturing is the most important mode to deal with, for the procession of manufacturing is designed for mass production in industry, which requires the manufacture keeps a stable level of high quality in industry production. Any small problem would lead to great economic loss in industry. Aiming at basic issues, specific parts of the production are supposed to change to shape the devices to a suitable constructure for the entire circuit, to meet the expectations on thermostability or high voltage resistance…
This kind of improvement is mostly based on the issues that happened in real production processions. The former research about power SiC device could be an example. In this case, with the sign of ablating in real production, further analyzation would be able to show the weakness on the oxide gate, with which the issue was quickly located, which was at the border between the gate oxygen and the field oxygen, the oxide layer too thin to hold the electric field. After the analyzation about all the influence which may lead to the thin of oxide layer, the method of improvement can be settled, which in this case is dividing the ion implantation into two steps, assuring the small ion concentration beside the border, which would cause less damage to the oxide layer [11].
4. Summary
This article generally summarises the most common failure modes of mosfets devices, then gives out some classifications on these failure modes, with the formation mechanism of each mode and example of actual failures, then based on the classification, summarising the common train of thought in dealing with each failure modes, with a specific example of each method, successfully in handling the issues caused by the failure of mosfets.
There is an overall view provided on dealing with the failure phenomenon for the engineers of cmos circuit design, which may introduce the basic information needed to deal with common failure modes that will happen in actual productions.
Though, there remains some shortcomings. Being limited by both time and the length, the summary of failure modes is too simple which may leak a number of failure modes existing in industry productions, in which way this article can still be improved by further analysations on other failure modes left out. Furthermore, the solution methods of these failure modes are too oversimplified, which may not suit to shape a feasible measure, also too specific for an overview, which may not suit to generate a comprehensive recognition on the methods. There might be a further improvement on these defects.
References
[1]. Zhang Xiaowen, Zhou Bin, Niu Hao, Lin Xiaoling, Review on the reliability evaluation of inherent failure mechanism of integrated circuits[J]. Integrated Circuits and Embedded Systems, 2024,(07):1-11.
[2]. Cai Xiaojie. Reliability and Failure Mechanism Analysis of GaN-based HEMT RF Power Devices[D]. Xidian University,2022.
[3]. Wang Mei. Power Cycle Reliability and Failure Mechanism of SiC MOSFET Devices with Different Gate Structures[D]. South China University of Technology, 2023.
[4]. Chen Jie, Deng Erping, Zhao Zixuan, Wu Yuxuan, Huang Yongzhang,. Failure Mechanism Analysis of SiC MOSFET under Different Aging Test Methods[J].TRANSACTIONS OF CHINA ELECTROTECHNICAL SOCIETY, 2020,(24):5105-5114.
[5]. Wang Yi.Failure Analysis of Power MOSFET and Design of Drive Circuit[D]. Wuhan University of Technology, 2014.
[6]. Ren Xinyu. Study on Failure Mechanism of Super-junction MOSFET under Electrical Stress, Thermal Stress and Humidity Stress[D]. University of Electronic Science and Technology of China,2023.
[7]. Jia Yifan. Study on the Trap Characteristics and Gate Oxide Reliability of 4H-SiC MOS structure[D]. Xidian University,2018.
[8]. Yuan Chunchun. Threshold Voltage Design and Reliability Study of SiC VDMOSFET[D]. Xidian University,2023.
[9]. Xin Weiping.Research of Ultra deep submicron SOC embedded Reliablity failure prediction technology[D]. Xidian University,2014.
[10]. Qian Yuchen. Research on Low Specific On-Resistance SGT MOS and Reliability[D]. University of Electronic Science and Technology of China,2024.
[11]. Wang Qihan. Research On Power SiC MOSFET Device Optimized Design and Reliability[D]. University of Electronic Science and Technology of China,2022.
Cite this article
Yang,Y. (2025). Basic Failure Modes of CMOS Devices and the Improvements. Applied and Computational Engineering,128,13-17.
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References
[1]. Zhang Xiaowen, Zhou Bin, Niu Hao, Lin Xiaoling, Review on the reliability evaluation of inherent failure mechanism of integrated circuits[J]. Integrated Circuits and Embedded Systems, 2024,(07):1-11.
[2]. Cai Xiaojie. Reliability and Failure Mechanism Analysis of GaN-based HEMT RF Power Devices[D]. Xidian University,2022.
[3]. Wang Mei. Power Cycle Reliability and Failure Mechanism of SiC MOSFET Devices with Different Gate Structures[D]. South China University of Technology, 2023.
[4]. Chen Jie, Deng Erping, Zhao Zixuan, Wu Yuxuan, Huang Yongzhang,. Failure Mechanism Analysis of SiC MOSFET under Different Aging Test Methods[J].TRANSACTIONS OF CHINA ELECTROTECHNICAL SOCIETY, 2020,(24):5105-5114.
[5]. Wang Yi.Failure Analysis of Power MOSFET and Design of Drive Circuit[D]. Wuhan University of Technology, 2014.
[6]. Ren Xinyu. Study on Failure Mechanism of Super-junction MOSFET under Electrical Stress, Thermal Stress and Humidity Stress[D]. University of Electronic Science and Technology of China,2023.
[7]. Jia Yifan. Study on the Trap Characteristics and Gate Oxide Reliability of 4H-SiC MOS structure[D]. Xidian University,2018.
[8]. Yuan Chunchun. Threshold Voltage Design and Reliability Study of SiC VDMOSFET[D]. Xidian University,2023.
[9]. Xin Weiping.Research of Ultra deep submicron SOC embedded Reliablity failure prediction technology[D]. Xidian University,2014.
[10]. Qian Yuchen. Research on Low Specific On-Resistance SGT MOS and Reliability[D]. University of Electronic Science and Technology of China,2024.
[11]. Wang Qihan. Research On Power SiC MOSFET Device Optimized Design and Reliability[D]. University of Electronic Science and Technology of China,2022.