Research on Low-Power Design Methods for Integrated Circuits
- 1 Heilongjiang University
* Author to whom correspondence should be addressed.
Abstract
The development of the integrated circuit industry has led to an increase in both the operating frequency and integration density of CMOS circuits, which has also resulted in a rising power density. To address the various adverse effects of increased power consumption on chip design, low-power design has become an essential aspect of chip development. This paper begins by examining the origins of power consumption and, based on this analysis, introduces low-power design techniques at the system architecture level, RTL level, as well as clock gating, multi-threshold voltage technology, and power gating techniques. These approaches allow designers to choose the optimal combination of power-saving techniques according to specific design needs, achieving lower power consumption without compromising performance.
Keywords
Integrated Circuit, Static Power Consumption, Dynamic Power Consumption, Low-Power Design
[1]. Pelgrom M.J.M.;Aad L..Matching Properties Of MOS Transistors[J].IEEE Journal of Solid-State Circuits,1989(5)
[2]. Massoud Pedram.Power minimization in IC design[J].ACM Transactions on Design Automation of Electronic Systems (TODAES),1996(1).
[3]. L. C, C. T. K, N. Pinto, V. P. B. R, S. Shankar and R. K. R, "Advanced CMOS VLSI Technology for Low Power Analog System Design with High Gain," 2022 IEEE International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE), Ballari, India, 2022, pp. 1-6, doi: 10.1109/ICDCECE53908.2022.9793203.
[4]. Yu Mei. Research on Low-Power Design Methods for SOC [D]. Fudan University, 2008..
[5]. Zhang Zhengkai. Research on Low-Power Design Methods for Digital Chips [D]. University of Electronic Science and Technology of China, 2008.
[6]. Binglong Zhang;Balasinski A..Hot-carrier effects on gate-induced-drain-leakage (GIDL) current in thin-film SOI/NMOSFET's[J].IEEE Electron Device Letters,1994(5).
[7]. Zhang Yu. Design and Verification of Low-Power Timer Based on MCU [D]. Xidian University, 2008.
[8]. V.G. Oklobdzija, "Digital System Clocking-High-Performance and Low-Power Aspects" in , New York, NY, USA:Wiley, 2003.
[9]. G. S. R. Srivatsava, P. Singh, S. Gaggar and S. K. Vishvakarma, "Dynamic power reduction through clock gating technique for low power memory applications," 2015 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT), Coimbatore, India, 2015, pp. 1-6, doi: 10.1109/ICECCT.2015.7226204.
[10]. Yu Xiqing, ed. Practical Guide to Application-Specific Integrated Circuit Design [M]. Zhejiang University Press, 2007.
Cite this article
Wang,S. (2025). Research on Low-Power Design Methods for Integrated Circuits. Applied and Computational Engineering,128,18-23.
Data availability
The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.
Disclaimer/Publisher's Note
The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of EWA Publishing and/or the editor(s). EWA Publishing and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.
About volume
Volume title: Proceedings of the 5th International Conference on Materials Chemistry and Environmental Engineering
© 2024 by the author(s). Licensee EWA Publishing, Oxford, UK. This article is an open access article distributed under the terms and
conditions of the Creative Commons Attribution (CC BY) license. Authors who
publish this series agree to the following terms:
1. Authors retain copyright and grant the series right of first publication with the work simultaneously licensed under a Creative Commons
Attribution License that allows others to share the work with an acknowledgment of the work's authorship and initial publication in this
series.
2. Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the series's published
version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgment of its initial
publication in this series.
3. Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and
during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See
Open access policy for details).