Introduction to machine leaning in electronic design automation (EDA)

Research Article
Open access

Introduction to machine leaning in electronic design automation (EDA)

Zeyu Tian 1*
  • 1 Electrical & Computer Engineering Department, The Grainger College of Engineering, University of Illinois Urbana-Champaign, Champaign, IL, USA    
  • *corresponding author zeyut2@illinois.edu
Published on 14 June 2023 | https://doi.org/10.54254/2755-2721/6/20230849
ACE Vol.6
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-915371-59-1
ISBN (Online): 978-1-915371-60-7

Abstract

The rapid growth of the intergraded circuit industry as predicted by Moore’s law has significantly increased the importance of efficient design processes. In addition, due to physical constraint, we will soon reach the limit of how small the size of the transistor can become, and the design processes will become more complex than ever. In order to cope with those challenges and introduce the product to the market within the time to market, the industry has been developing ways to apply machine learning to concurrent EDA tools. This paper will aim to introduce how machine learning is applied to varies processes of electronic design and how they improve the current EDA tools. We will also show the limitations and opportunities of ML based EDA tools and provide a rough idea of the potential future to those who are looking into this area.

Keywords:

Electronic Design Automation, Machine Learning, Reinforcement Learning, Chip placement, Routing, Electronic Design.

Tian,Z. (2023). Introduction to machine leaning in electronic design automation (EDA). Applied and Computational Engineering,6,415-421.
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References

[1]. Lopera, D. S., Servadei, L., Kiprit, G. N., Hazra, S., Wille, R., & Ecker, W. (2021). A Survey of Graph Neural Networks for Electronic Design Automation. 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), Machine Learning for CAD (MLCAD), 2021 ACM/IEEE 3rd Workshop On, 1–6.

[2]. D., S. A. (2021). Electronic Design Automation Tools: A Review. IUP Journal of Electrical & Electronics Engineering, 14(4), 27–32.

[3]. NVIDIA. (2022). Insights from NVIDIA Research. Retrieved from https://www.nvidia.com/en-us/on-demand/session/gtcspring22-s42013/?ncid=afm-chs-44270&ranMID=44270&ranEAID=kXQk6%2AivFEQ&ranSiteID=kXQk6.ivFEQ-jNcbNKs0ktck5rPkTF4B.Q.

[4]. Mirhoseini, A., Goldie, A., Yazgan, M. et al. (2021). A graph placement methodology for fast chip design. Nature 594, 207–212.

[5]. C.-K. Cheng, A. B. Kahng, I. Kang, and L. Wang, “RePlAce: Advancing solution quality and routability validation in global placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 9, pp. 1717–1730, 2019.

[6]. Budak, A. F., Jiang, Z., Zhu, K., Mirhoseini, A., Goldie, A., & Pan, D. Z. (2022). Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Design Automation Conference (ASP-DAC), 2022 27th Asia and South Pacific, 500–505.

[7]. Lu, Y. C., Pentapati, S., & Lim, S. K. (2020). Vlsi placement optimization using graph neural networks. In 34th Advances in Neural Information Processing Systems (NeurIPS) Workshop on ML for Systems.

[8]. De Amorim, R. C., & Mirkin, B. (2012). Minkowski metric, feature weighting and anomalous cluster initializing in K-Means clustering. Pattern Recognition, 45(3), 1061-1075.

[9]. Kirby, R., Godil, S., Roy, R., & Catanzaro, B. (2019). Congestionnet: Routing congestion prediction using deep graph neural networks. In 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 217-222). IEEE.

[10]. V. A. Chhabria, Y. Zhang, H. Ren, B. Keller, B. Khailany and S. S. Sapatnekar. (2021). "MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1825-1828.

[11]. Ronneberger, O., Fischer, P., & Brox, T. (2015). U-net: Convolutional networks for biomedical image segmentation. In International Conference on Medical image computing and computer-assisted intervention (pp. 234-241). Springer, Cham.

[12]. Ren, H., Kokai, G. F., Turner, W. J., & Ku, T. S. (2020). ParaGraph: Layout parasitics and device parameter prediction using graph neural networks. In 2020 57th ACM/IEEE Design Automation Conference (DAC) (pp. 1-6). IEEE.

[13]. K. Liu, J. J. Zhang, B. Tan and D. Feng. (2021). "Can We Trust Machine Learning for Electronic Design Automation?," 2021 IEEE 34th International System-on-Chip Conference (SOCC), pp. 135-140.

Cite this article

Tian,Z. (2023). Introduction to machine leaning in electronic design automation (EDA). Applied and Computational Engineering,6,415-421.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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About volume

Volume title: Proceedings of the 3rd International Conference on Signal Processing and Machine Learning

ISBN：978-1-915371-59-1(Print) / 978-1-915371-60-7(Online)
Editor：Omer Burak Istanbullu
Conference website: http://www.confspml.org
Conference date: 25 February 2023
Series: Applied and Computational Engineering
Volume number: Vol.6
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. Lopera, D. S., Servadei, L., Kiprit, G. N., Hazra, S., Wille, R., & Ecker, W. (2021). A Survey of Graph Neural Networks for Electronic Design Automation. 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), Machine Learning for CAD (MLCAD), 2021 ACM/IEEE 3rd Workshop On, 1–6.

[2]. D., S. A. (2021). Electronic Design Automation Tools: A Review. IUP Journal of Electrical & Electronics Engineering, 14(4), 27–32.

[3]. NVIDIA. (2022). Insights from NVIDIA Research. Retrieved from https://www.nvidia.com/en-us/on-demand/session/gtcspring22-s42013/?ncid=afm-chs-44270&ranMID=44270&ranEAID=kXQk6%2AivFEQ&ranSiteID=kXQk6.ivFEQ-jNcbNKs0ktck5rPkTF4B.Q.

[4]. Mirhoseini, A., Goldie, A., Yazgan, M. et al. (2021). A graph placement methodology for fast chip design. Nature 594, 207–212.

[5]. C.-K. Cheng, A. B. Kahng, I. Kang, and L. Wang, “RePlAce: Advancing solution quality and routability validation in global placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 9, pp. 1717–1730, 2019.

[6]. Budak, A. F., Jiang, Z., Zhu, K., Mirhoseini, A., Goldie, A., & Pan, D. Z. (2022). Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Design Automation Conference (ASP-DAC), 2022 27th Asia and South Pacific, 500–505.

[7]. Lu, Y. C., Pentapati, S., & Lim, S. K. (2020). Vlsi placement optimization using graph neural networks. In 34th Advances in Neural Information Processing Systems (NeurIPS) Workshop on ML for Systems.

[8]. De Amorim, R. C., & Mirkin, B. (2012). Minkowski metric, feature weighting and anomalous cluster initializing in K-Means clustering. Pattern Recognition, 45(3), 1061-1075.

[9]. Kirby, R., Godil, S., Roy, R., & Catanzaro, B. (2019). Congestionnet: Routing congestion prediction using deep graph neural networks. In 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 217-222). IEEE.

[10]. V. A. Chhabria, Y. Zhang, H. Ren, B. Keller, B. Khailany and S. S. Sapatnekar. (2021). "MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1825-1828.

[11]. Ronneberger, O., Fischer, P., & Brox, T. (2015). U-net: Convolutional networks for biomedical image segmentation. In International Conference on Medical image computing and computer-assisted intervention (pp. 234-241). Springer, Cham.

[12]. Ren, H., Kokai, G. F., Turner, W. J., & Ku, T. S. (2020). ParaGraph: Layout parasitics and device parameter prediction using graph neural networks. In 2020 57th ACM/IEEE Design Automation Conference (DAC) (pp. 1-6). IEEE.

[13]. K. Liu, J. J. Zhang, B. Tan and D. Feng. (2021). "Can We Trust Machine Learning for Electronic Design Automation?," 2021 IEEE 34th International System-on-Chip Conference (SOCC), pp. 135-140.

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