References
[1]. S. Wong, F. Duarte and S. Vassiliadis, "A hardware cache memcpy accelerator," 2006 IEEE International Conference on Field Programmable Technology, Bangkok, Thailand, 2006, pp. 141-148.
[2]. T. Kalkhof and A. Koch, "Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems," 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Belfast, United Kingdom, 2022, pp. 225-234.
[3]. "ISO/IEC/IEEE International Standard for Information technology--Microprocessor systems--Control and Status Registers (CSR) Architecture for microcomputer buses," in ISO/IEC 13213: 1994, vol., no., pp.1-144, 5 Oct. 1994.
[4]. B. Zeng, “What is Direct Memory Access (DMA)? - Definition from WhatIs.com,” WhatIs.com, 2022. https://www.techtarget.com/whatis/definition/Direct-Memory-Access-DMA
[5]. W. Su, L. Wang, M. Su and S. Liu, "A Processor-DMA-Based Memory Copy Hardware Accelerator," 2011 IEEE Sixth International Conference on Networking, Architecture, and Storage, Dalian, China, 2011, pp. 225-229.
[6]. F. Duarte and S. Wong, "Cache-Based Memory Copy Hardware Accelerator for Multicore Systems," in IEEE Transactions on Computers, vol. 59, no. 11, pp. 1494-1507, Nov. 2010.
[7]. S. Vassiliadis, F. Duarte and S. Wong, "A Load/Store Unit for a Memcpy Hardware Accelerator," 2007 International Conference on Field Programmable Logic and Applications, Amsterdam, Netherlands, 2007, pp. 537-541.
[8]. U. S. Solangi, M. Ibtesam, M. A. Ansari, J. Kim, and S. Park, “Test Architecture for Systolic Array of Edge-Based AI Accelerator,” IEEE Access, vol. 9, pp. 96700–96710, 2021.
[9]. F. Duarte and S. Wong, "A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies," 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP), Montreal, QC, Canada, 2007, pp. 397-402.
[10]. W. Muła and D. Lemire, “Base64 encoding and decoding at almost the speed of a memory copy,” Software: Practice and Experience, vol. 50, no. 2, pp. 89–97, Nov. 2019.
Cite this article
Shen,S. (2023). Theoretical analysis and comparison of memory copy accelerators. Applied and Computational Engineering,9,295-302.
Data availability
The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.
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References
[1]. S. Wong, F. Duarte and S. Vassiliadis, "A hardware cache memcpy accelerator," 2006 IEEE International Conference on Field Programmable Technology, Bangkok, Thailand, 2006, pp. 141-148.
[2]. T. Kalkhof and A. Koch, "Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems," 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Belfast, United Kingdom, 2022, pp. 225-234.
[3]. "ISO/IEC/IEEE International Standard for Information technology--Microprocessor systems--Control and Status Registers (CSR) Architecture for microcomputer buses," in ISO/IEC 13213: 1994, vol., no., pp.1-144, 5 Oct. 1994.
[4]. B. Zeng, “What is Direct Memory Access (DMA)? - Definition from WhatIs.com,” WhatIs.com, 2022. https://www.techtarget.com/whatis/definition/Direct-Memory-Access-DMA
[5]. W. Su, L. Wang, M. Su and S. Liu, "A Processor-DMA-Based Memory Copy Hardware Accelerator," 2011 IEEE Sixth International Conference on Networking, Architecture, and Storage, Dalian, China, 2011, pp. 225-229.
[6]. F. Duarte and S. Wong, "Cache-Based Memory Copy Hardware Accelerator for Multicore Systems," in IEEE Transactions on Computers, vol. 59, no. 11, pp. 1494-1507, Nov. 2010.
[7]. S. Vassiliadis, F. Duarte and S. Wong, "A Load/Store Unit for a Memcpy Hardware Accelerator," 2007 International Conference on Field Programmable Logic and Applications, Amsterdam, Netherlands, 2007, pp. 537-541.
[8]. U. S. Solangi, M. Ibtesam, M. A. Ansari, J. Kim, and S. Park, “Test Architecture for Systolic Array of Edge-Based AI Accelerator,” IEEE Access, vol. 9, pp. 96700–96710, 2021.
[9]. F. Duarte and S. Wong, "A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies," 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP), Montreal, QC, Canada, 2007, pp. 397-402.
[10]. W. Muła and D. Lemire, “Base64 encoding and decoding at almost the speed of a memory copy,” Software: Practice and Experience, vol. 50, no. 2, pp. 89–97, Nov. 2019.