Download pdf
Design a 5-stage pipeline RISC-V CPU and optimise its ALU
- 1 University of Electronic Science and Technology of China
* Author to whom correspondence should be addressed.
Abstract
The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.
Keywords
RISC-V, Instructions, ALU, Testbench
[1]. Lu T. 2021. A Survey on RISC-V Security: Hardware and Architecture. arXiv.org. [Online]. Available at: https://arxiv.org/abs/2107.04175v1.
[2]. Cui E, Li T, Wei Q. 2023. RISC-V Instruction Set Architecture Extensions: A Survey. IEEE Access. 11: 24696-24711.
[3]. Sharma M, Bhatnagar E, Puri K, Mitra A, Agarwal J. 2022. A survey of RISC-V CPU for IoT applications. Available at SSRN 4033491
[4]. Waterman A, Lee Y, Avizienis R, Patterson DA, Asanovic K. 2015. The RISC-V instruction set manual volume II: Privileged architecture version 1.7. EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-49.
[5]. Dennis DK, Priyam A, Virk SS, Agrawal S, Sharma T, Mondal A and Ray KC. 2017, December. Single cycle RISC-V microarchitecture processor and its FPGA prototype. In: Proceedings of the 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, pp. 1-5.
[6]. Avinash NJ, Mishra I, Ghorpade TC, Lokesh M, Nishanth H, Kumar M. 2023, January. Design and Implementation of 32-Bit MIPS RISC Processor with Flexible 5-Stage Pipelining and Dynamic Thermal Control. In: Proceedings of the 2023 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE), Bengaluru, India, pp. 846-849.
[7]. Lai J-Y, Chen C-A, Chen S-L, Su C-Y. 2021. Implement 32-bit RISC-V Architecture Processor using Verilog HDL in: Proceedings of the 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Hualien City, Taiwan, pp. 1-2.
[8]. Miao J, Li S. 2017. A novel implementation of a 4-bit carry look-ahead adder in Proceedings of the 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, pp. 1-2.
[9]. Tiwari P, Kumar A. 2021. A 4-bit Barrel Shifter Design using Diverse Logic Styles. In: Proceedings of the 2021 First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT), Meerut, India, pp. 131-134.
[10]. Govekar D, Amonkar A. 2017. Design and implementation of high-speed modified Booth multiplier using hybrid adder. In: Proceedings of the 2017 International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, pp. 138-143.
Cite this article
Deng,L. (2024). Design a 5-stage pipeline RISC-V CPU and optimise its ALU. Applied and Computational Engineering,34,237-244.
Data availability
The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.
Disclaimer/Publisher's Note
The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of EWA Publishing and/or the editor(s). EWA Publishing and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.
About volume
Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation
© 2024 by the author(s). Licensee EWA Publishing, Oxford, UK. This article is an open access article distributed under the terms and
conditions of the Creative Commons Attribution (CC BY) license. Authors who
publish this series agree to the following terms:
1. Authors retain copyright and grant the series right of first publication with the work simultaneously licensed under a Creative Commons
Attribution License that allows others to share the work with an acknowledgment of the work's authorship and initial publication in this
series.
2. Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the series's published
version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgment of its initial
publication in this series.
3. Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and
during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See
Open access policy for details).