Optimizing multiplier design for enhanced processor performance

Research Article
Open access

Optimizing multiplier design for enhanced processor performance

Bilun Wu 1 , Zeyu Zhang 2*
  • 1 Beijing University of Posts and Telecommunications    
  • 2 Zhengzhou University of Light Industry    
  • *corresponding author Zhangzeyu@zzuli.edu.cn
Published on 7 February 2024 | https://doi.org/10.54254/2755-2721/38/20230564
ACE Vol.38
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-301-2
ISBN (Online): 978-1-83558-302-9

Abstract

In processor design, the multiplier serves as a critical component whose operational speed and efficiency directly impact the performance of the processor. To meet the demands of rapidly advancing technology, enhancing processor performance is of paramount importance. The crux of multiplier design lies in reducing the count of partial products and compressing them. This paper presents the design of a multiplier that utilizes the Booth algorithm and the Wallace tree structure for optimization, along with the incorporation of registers for secondary pipeline processing to further elevate efficiency. The Booth algorithm selects the base-4 Booth algorithm, effectively reducing the count of partial products and mitigating the optimization efficiency reduction caused by circuit complexity. The Wallace tree structure employs a combination of 3-2 and 4-2 compressors, resulting in decreased resource consumption and reduced critical path delays. This paper outlines a step-by-step introduction to these three optimization methods and conducts simulations and tests on the current multiplier after each optimization step. Through simulation analysis, this paper confirms the success of the design and provides insights and outcomes to the current field of multiplier optimization, aiming to ultimately drive advancements in processor performance.

Keywords:

Multiplier Optimization, Processor Performance, Booth Algorithm, Wallace Tree Structure

Wu,B.;Zhang,Z. (2024). Optimizing multiplier design for enhanced processor performance. Applied and Computational Engineering,38,280-287.
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References

[1]. Sakali Raghavendra Kumar,Veeramachaneni Sreehari & Mahammad Sk Noor.(2023).Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs. Integration.

[2]. Saleh Omar S..(2023).RCAM: Resource Constraint Approximate Multiplier Design for Deep Convolutional Neural Network Accelerator. SN Computer Science(4).

[3]. Barma Venkata RamaLakshmi & Fazal Noorbasha.(2021).FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm. International Journal of Performability Engineering(6).

[4]. Tamilselvan S,Dharani S,Ramesh R & HemaPriya K.(2021).Implementation of efficient MAC for DSP applications using Modified Booth Encoding algorithm technique. IOP Conference Series: Materials Science and Engineering(1).

[5]. Ponraj Jeyakumar,Jeyabharath R.,Veena P. & Srihari Tharumar.(2023).High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system. Integration.

[6]. Malathi L.,Bharathi A. & Jayanthi A. N..(2022).RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications. International Journal of Electronics(10).

[7]. Shekari Mahnaz,García David Vállez,Collij Lyduine E.,Heeman Fiona,RoéVellvé Núria,Bullich Santiago... & Gispert Juan Domingo.(2022).Evaluating the sensitivity of Centiloid quantification to pipeline design and image resoloution. Alzheimer's & Dementia.

[8]. Hemalatha K N & Sangeetha B G.(2022).Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic. International Journal of Engineering and Manufacturing(IJEM)(4).

[9]. Mummudi Murasu M,Sujith Sanjana,Anita Angeline A,Sasi Priya P. & Kanchana Bhaaskaran V S.(2021).High Performance Wallace Tree Multiplier Using Majority Gate Based Adders. IOP Conference Series: Materials Science and Engineering(1).

[10]. Vaibhavi Solanki,A. D. Darji & Harikrishna Singapuri.(2021).Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach. Circuits, Systems, and Signal Processing(9).

Cite this article

Wu,B.;Zhang,Z. (2024). Optimizing multiplier design for enhanced processor performance. Applied and Computational Engineering,38,280-287.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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About volume

Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation

ISBN：978-1-83558-301-2(Print) / 978-1-83558-302-9(Online)
Editor：Mustafa İSTANBULLU
Conference website: https://2023.confmla.org/
Conference date: 18 October 2023
Series: Applied and Computational Engineering
Volume number: Vol.38
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. Sakali Raghavendra Kumar,Veeramachaneni Sreehari & Mahammad Sk Noor.(2023).Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs. Integration.

[2]. Saleh Omar S..(2023).RCAM: Resource Constraint Approximate Multiplier Design for Deep Convolutional Neural Network Accelerator. SN Computer Science(4).

[3]. Barma Venkata RamaLakshmi & Fazal Noorbasha.(2021).FPGA Implementation of Optimized Radix 4 and Radix 8 Booth Algorithm. International Journal of Performability Engineering(6).

[4]. Tamilselvan S,Dharani S,Ramesh R & HemaPriya K.(2021).Implementation of efficient MAC for DSP applications using Modified Booth Encoding algorithm technique. IOP Conference Series: Materials Science and Engineering(1).

[5]. Ponraj Jeyakumar,Jeyabharath R.,Veena P. & Srihari Tharumar.(2023).High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system. Integration.

[6]. Malathi L.,Bharathi A. & Jayanthi A. N..(2022).RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications. International Journal of Electronics(10).

[7]. Shekari Mahnaz,García David Vállez,Collij Lyduine E.,Heeman Fiona,RoéVellvé Núria,Bullich Santiago... & Gispert Juan Domingo.(2022).Evaluating the sensitivity of Centiloid quantification to pipeline design and image resoloution. Alzheimer's & Dementia.

[8]. Hemalatha K N & Sangeetha B G.(2022).Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic. International Journal of Engineering and Manufacturing(IJEM)(4).

[9]. Mummudi Murasu M,Sujith Sanjana,Anita Angeline A,Sasi Priya P. & Kanchana Bhaaskaran V S.(2021).High Performance Wallace Tree Multiplier Using Majority Gate Based Adders. IOP Conference Series: Materials Science and Engineering(1).

[10]. Vaibhavi Solanki,A. D. Darji & Harikrishna Singapuri.(2021).Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach. Circuits, Systems, and Signal Processing(9).

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