Download pdf
Advancements in VLSI low-power design: Strategies and optimization techniques
- 1 Shandong University
* Author to whom correspondence should be addressed.
Abstract
As production technology advances, integrated circuits are increasing in size, leading to a corresponding rise in power consumption if not properly optimized. Consequently, the optimization of integrated circuit power consumption has gained paramount significance. This paper provides an overview of the theoretical and research developments in Very Large Scale Integration (VLSI) low-power design. Initially, the paper delves into the components of VLSI power consumption, elucidating the origins of various power consumption types and the factors influencing their magnitude. Subsequently, existing power reduction technologies are examined, including transistor-level optimization, gate-level optimization, and system-level power optimization. The principles, applicable power consumption types, as well as their respective advantages and drawbacks are analysed. The paper also introduces methods for evaluating VLSI power consumption and summarizes the characteristics, advantages, and disadvantages of high-level power estimation and low-level power estimation. Ultimately, it underscores the importance of considering multiple power optimization strategies during VLSI design and discusses research approaches for achieving low power consumption. This comprehensive exploration contributes to the enhancement and optimization of VLSI design efforts.
Keywords
VLSI, CMOS, Power Consumption, Integrated Circuit
[1]. Zhang Bowwen. Low power physical design analysis of nanoscale VLSI chips. Communication Power Technology, 2020, 37(6): 2.
[2]. Lai Lingqing, Li Dongkai. A review of Cmos static power optimization and estimation methods. Heilongjiang Science and Technology Information 2022, (27).
[3]. Yang RuiRui, He Tao, Tang WeiWen, Fan WeiLi. Ultra-low power design method for Soc systems. Communication Technology, 2018, 51(4): 6.
[4]. Ali I, Jo Y I, Lee S, et al. Reducing dynamic power consumption in mixed-critical real-time systems. Applied Sciences, 2020, 10(20): 7256.
[5]. Kursun E, Ghiasi S, Sarrafzadeh M. Transistor level budgeting for power optimization. International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003.(Cat. No. 03EX720). IEEE, 2004: 116-121.
[6]. Tripathi A N, Rajawat A. System-Level Leakage Power Estimation Model for ASIC Designs. Advances in Electrical and Electronic Engineering, 2018, 16(3): 361-366.
[7]. Ohm V J, Leeser M. A Graph-Based Power Estimation Method for Combinational CMOS Circuits. 2022
[8]. Varadharajan S K, Nallasamy V. Low power VLSI circuits design strategies and methodologies: A literature review. 2017 Conference on Emerging Devices and Smart Systems (ICEDSS). IEEE, 2017: 245-251.
[9]. Jung J, Jiang I H R, Nam G J, et al. OpenDesign Flow Database: The infrastructure for VLSI design and design automation research. 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2016: 1-6.
[10]. Gensuke G. Special issue on low-power high-performance VLSI processors and technologies. IEICE transactions on electronics, 2001, 84(2): 129-130.
[11]. Mukherjee D, Reddy B V R. Algorithm design, software simulation and mathematical modelling of subthreshold leakage current in CMOS circuits. International Journal of Computational Complexity and Intelligent Algorithms, 2019, 1(2): 129-144.
[12]. Kaur K, Noor A. Strategies & methodologies for low power VLSI designs: A review. International Journal of Advances in Engineering & Technology, 2011, 1(2): 159.
[13]. Khailany B, Venkatesan R, Clemons J, et al. A modular digital VLSI flow for high-productivity SoC design. Proceedings of the 55th Annual Design Automation Conference. 2018: 1-6.
Cite this article
Shan,T. (2024). Advancements in VLSI low-power design: Strategies and optimization techniques. Applied and Computational Engineering,41,22-28.
Data availability
The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.
Disclaimer/Publisher's Note
The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of EWA Publishing and/or the editor(s). EWA Publishing and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.
About volume
Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation
© 2024 by the author(s). Licensee EWA Publishing, Oxford, UK. This article is an open access article distributed under the terms and
conditions of the Creative Commons Attribution (CC BY) license. Authors who
publish this series agree to the following terms:
1. Authors retain copyright and grant the series right of first publication with the work simultaneously licensed under a Creative Commons
Attribution License that allows others to share the work with an acknowledgment of the work's authorship and initial publication in this
series.
2. Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the series's published
version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgment of its initial
publication in this series.
3. Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and
during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See
Open access policy for details).