Design and optimization of CMOS based 4-bit comparator

Research Article
Open access

Design and optimization of CMOS based 4-bit comparator

Ran Yan 1*
  • 1 Southwest Jiaotong University    
  • *corresponding author 2021114236@my.swjtu.edu.cn
Published on 22 February 2024 | https://doi.org/10.54254/2755-2721/41/20230707
ACE Vol.41
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-307-4
ISBN (Online): 978-1-83558-308-1

Abstract

The paper primarily focuses on optimizing circuit delay and energy consumption, specifically in gate-level circuits. Three methods are employed for circuit optimization. The first method aims to minimize transistor usage to reduce both delay and energy consumption. The second method involves prioritizing logic gates based on underlying hardware, favoring simpler circuit structures whenever possible, given that our design primarily revolves around logic gates. The third method entails adjusting the number of stages to enhance delay optimization. To validate these rules, three distinct circuits were designed to implement a 4-bit absolute value comparator, each corresponding to one of the rules. Through simulation, calculation, and comparison, the best circuit was identified, providing validation for the rules. The second part of the paper shifts its focus towards optimizing delay and energy consumption by adjusting the sizing of logic gates and the supply voltage to achieve optimal overall performance. In conclusion, further research is needed to corroborate these three rules and identify additional rules, laying the foundation for intelligent circuit optimization.

Keywords:

Delay, Energy Consumption, Sizing, Supply Voltage

Yan,R. (2024). Design and optimization of CMOS based 4-bit comparator. Applied and Computational Engineering,41,29-42.
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References

[1]. Lundstrom Mark, S and Alam Muhammad. “Moore’s law: The journey ahead, Science (New York, N.Y.) “. 2022, vol 378, no. 6621, pp. 722-723.

[2]. Chenyu Du, Yucheng Guo, Junchao Zhang. “A Low Energy Depletion CMOS Transistor-based 4-bit Absolute-value Detector”, Journal of Physics: Conference Series, 2023.

[3]. D. N. Mukherjee, S. Panda and B. Maji, “Design of low power 12-bit magnitude comparator,” 2017 Devices for Integrated Circuit (DevIC), Kalyani, India, 2017, pp. 103-109.

[4]. P. Das, P. J. Edavoor, S. Raveendran and A. D. Rahulkar, “Design and implementation of computationally efficient architecture of PID based motion controller for robotic land navigation system in FPGA,” 2017 Conference on Information and Communication Technology (CICT), Gwalior, India, 2017, pp. 1-6.

[5]. Chi-Chang Wang and Jin-Chuan Wu, “A 3.3-V/5-V low power TTL-to-CMOS input buffer,” in IEEE Journal of Solid-State Circuits, 1998, vol. 33, no. 4, pp. 598-603.

[6]. A. E. Engin, “Passive Multiport RC Model Extraction for Through Silicon Via Interconnects in 3-D ICs,” in IEEE Transactions on Electromagnetic Compatibility, 2014, vol. 56, no. 3, pp. 646-652.

[7]. S. Arora, P. T. Balsara and D. K. Bhatia, “Digital implementation of constant power load (CPL), active resistive load, constant current load and combinations,” 2016 IEEE Dallas Circuits and Systems Conference (DCAS), Arlington, TX, USA, 2016, pp. 1-4.

[8]. H. Rahman, C. Chakrabarti. “An efficient control point insertion technique for leakage reduction of scaled CMOS circuits”, IEEE Transactions on Circuits and Systems II: Express Briefs, 2005.

[9]. Akashi Satoh. “Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia”, Lecture Notes in Computer Science, 2003.

[10]. Yung-Chih Chen. “Tree-Based Logic Encryption for Resisting SAT Attack”, 2017 IEEE 26th Asian Test Symposium (ATS), 2017.

Cite this article

Yan,R. (2024). Design and optimization of CMOS based 4-bit comparator. Applied and Computational Engineering,41,29-42.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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About volume

Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation

ISBN：978-1-83558-307-4(Print) / 978-1-83558-308-1(Online)
Editor：Mustafa İSTANBULLU
Conference website: https://2023.confmla.org/
Conference date: 18 October 2023
Series: Applied and Computational Engineering
Volume number: Vol.41
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. Lundstrom Mark, S and Alam Muhammad. “Moore’s law: The journey ahead, Science (New York, N.Y.) “. 2022, vol 378, no. 6621, pp. 722-723.

[2]. Chenyu Du, Yucheng Guo, Junchao Zhang. “A Low Energy Depletion CMOS Transistor-based 4-bit Absolute-value Detector”, Journal of Physics: Conference Series, 2023.

[3]. D. N. Mukherjee, S. Panda and B. Maji, “Design of low power 12-bit magnitude comparator,” 2017 Devices for Integrated Circuit (DevIC), Kalyani, India, 2017, pp. 103-109.

[4]. P. Das, P. J. Edavoor, S. Raveendran and A. D. Rahulkar, “Design and implementation of computationally efficient architecture of PID based motion controller for robotic land navigation system in FPGA,” 2017 Conference on Information and Communication Technology (CICT), Gwalior, India, 2017, pp. 1-6.

[5]. Chi-Chang Wang and Jin-Chuan Wu, “A 3.3-V/5-V low power TTL-to-CMOS input buffer,” in IEEE Journal of Solid-State Circuits, 1998, vol. 33, no. 4, pp. 598-603.

[6]. A. E. Engin, “Passive Multiport RC Model Extraction for Through Silicon Via Interconnects in 3-D ICs,” in IEEE Transactions on Electromagnetic Compatibility, 2014, vol. 56, no. 3, pp. 646-652.

[7]. S. Arora, P. T. Balsara and D. K. Bhatia, “Digital implementation of constant power load (CPL), active resistive load, constant current load and combinations,” 2016 IEEE Dallas Circuits and Systems Conference (DCAS), Arlington, TX, USA, 2016, pp. 1-4.

[8]. H. Rahman, C. Chakrabarti. “An efficient control point insertion technique for leakage reduction of scaled CMOS circuits”, IEEE Transactions on Circuits and Systems II: Express Briefs, 2005.

[9]. Akashi Satoh. “Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia”, Lecture Notes in Computer Science, 2003.

[10]. Yung-Chih Chen. “Tree-Based Logic Encryption for Resisting SAT Attack”, 2017 IEEE 26th Asian Test Symposium (ATS), 2017.

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