A verilog design for cascading a large-capacity asynchronous FIFO with a synchronous FIFO

Research Article
Open access

A verilog design for cascading a large-capacity asynchronous FIFO with a synchronous FIFO

Keyu Liu 1*
  • 1 South China University of Technology    
  • *corresponding author 202264710491@mail.scut.edu.cn
Published on 23 October 2023 | https://doi.org/10.54254/2755-2721/14/20230754
ACE Vol.14
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-019-6
ISBN (Online): 978-1-83558-020-2

Abstract

In modern large scale ASIC designs, multiple clock systems are often involved, which can create problems with data transfer in different clock domains. A practical solution to this problem is the use of asynchronous FIFOs (First In First Out) for buffering the transfer of data from different clock domains. A high-capacity asynchronous FIFO cascaded with a synchronous FIFO is designed based on a conventional asynchronous FIFO using the Verilog language. The input data is processed across the clock domain by the asynchronous FIFO, and the data output from the asynchronous FIFO is cached and output again by the synchronous FIFO. The module increases the FIFO depth while enabling data to be transferred across the clock domain. The simulation is completed within the Modelsim software which accordingly verifies the two main roles of the FIFO in processing data, namely the cross-clock domain and the data caching function. Simulation results show that the asynchronous FIFO data is written and read correctly and that the empty/full flag signal is correct.

Keywords:

asynchronous FIFO, synchronous FIFO, verilog language

Liu,K. (2023). A verilog design for cascading a large-capacity asynchronous FIFO with a synchronous FIFO. Applied and Computational Engineering,14,25-30.
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References

[1]. Acharya D, Mehta U S. Performance Analysis of RTL to GDS-II Flow in Opensource Tool Qflow and Commercial Tool Cadence Encounter for Synchronous FIFO[C]//2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON). IEEE, 2022: 199-204.

[2]. Kumar P, Moud R. DESIGNING AND VERIFICATION OF ASYNCHRONOUS FIFO[J]. International Journal of Advanced Research in Computer Science, 2022, 13.

[3]. Abasaheb S A, Kamatchi S. Design of Mesochronous Dual Clock Fifo Buffer with Modified Synchronizer Circuit[C]//2022 6th International Conference on Electronics, Communication and Aerospace Technology. IEEE, 2022: 1-7.

[4]. Khosla M. Coverage of Meta-Stability Using Formal Verification in Asynchronous Gray Code FIFO[C]//2022 2nd International Conference on Intelligent Technologies (CONIT). IEEE, 2022: 1-8.

[5]. Khosla M. Coverage of Meta-Stability Using Formal Verification in Asynchronous Gray Code FIFO[C]//2022 2nd International Conference on Intelligent Technologies (CONIT). IEEE, 2022: 1-8.

[6]. Li J, Yang L, Feng X, et al. UART Controller with FIFO Buffer Function Based on APB Bus[C]//2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID). IEEE, 2022: 1-4.

[7]. de Castro2 Guowei R A L, Yazicigil Y C J R, Joshi A C V V A. FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption[J].

[8]. Yamamoto K, Fukuhara A, Nishi H. Hardware Implementation of MQTT Broker and Precise Time Synchronization Using IoT Devices[J]. IEEJ Transactions on Electrical and Electronic Engineering, 2022, 17(2): 209-217.

[9]. Hsia S C, Wang S H, Kuo T T. VLSI architecture and implementation of HDR camera signal processor[J]. Journal of Real-Time Image Processing, 2023, 20(1): 6.

[10]. Nowosielski A, Reginia P. Digital Wah-Wah Guitar Effect Controlled by Mouth Movements[C]//Computer Vision and Graphics: Proceedings of the International Conference on Computer Vision and Graphics ICCVG 2022. Cham: Springer Nature Switzerland, 2023: 31-39.

Cite this article

Liu,K. (2023). A verilog design for cascading a large-capacity asynchronous FIFO with a synchronous FIFO. Applied and Computational Engineering,14,25-30.

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About volume

Volume title: Proceedings of the 5th International Conference on Computing and Data Science

ISBN：978-1-83558-019-6(Print) / 978-1-83558-020-2(Online)
Editor：Alan Wang, Marwan Omar, Roman Bauer
Conference website: https://2023.confcds.org/
Conference date: 14 July 2023
Series: Applied and Computational Engineering
Volume number: Vol.14
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. Acharya D, Mehta U S. Performance Analysis of RTL to GDS-II Flow in Opensource Tool Qflow and Commercial Tool Cadence Encounter for Synchronous FIFO[C]//2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON). IEEE, 2022: 199-204.

[2]. Kumar P, Moud R. DESIGNING AND VERIFICATION OF ASYNCHRONOUS FIFO[J]. International Journal of Advanced Research in Computer Science, 2022, 13.

[3]. Abasaheb S A, Kamatchi S. Design of Mesochronous Dual Clock Fifo Buffer with Modified Synchronizer Circuit[C]//2022 6th International Conference on Electronics, Communication and Aerospace Technology. IEEE, 2022: 1-7.

[4]. Khosla M. Coverage of Meta-Stability Using Formal Verification in Asynchronous Gray Code FIFO[C]//2022 2nd International Conference on Intelligent Technologies (CONIT). IEEE, 2022: 1-8.

[5]. Khosla M. Coverage of Meta-Stability Using Formal Verification in Asynchronous Gray Code FIFO[C]//2022 2nd International Conference on Intelligent Technologies (CONIT). IEEE, 2022: 1-8.

[6]. Li J, Yang L, Feng X, et al. UART Controller with FIFO Buffer Function Based on APB Bus[C]//2022 IEEE 16th International Conference on Anti-counterfeiting, Security, and Identification (ASID). IEEE, 2022: 1-4.

[7]. de Castro2 Guowei R A L, Yazicigil Y C J R, Joshi A C V V A. FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption[J].

[8]. Yamamoto K, Fukuhara A, Nishi H. Hardware Implementation of MQTT Broker and Precise Time Synchronization Using IoT Devices[J]. IEEJ Transactions on Electrical and Electronic Engineering, 2022, 17(2): 209-217.

[9]. Hsia S C, Wang S H, Kuo T T. VLSI architecture and implementation of HDR camera signal processor[J]. Journal of Real-Time Image Processing, 2023, 20(1): 6.

[10]. Nowosielski A, Reginia P. Digital Wah-Wah Guitar Effect Controlled by Mouth Movements[C]//Computer Vision and Graphics: Proceedings of the International Conference on Computer Vision and Graphics ICCVG 2022. Cham: Springer Nature Switzerland, 2023: 31-39.

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