A 6-bit absolute value detector based on MOSFET and PTL structure

Research Article
Open access

A 6-bit absolute value detector based on MOSFET and PTL structure

Yucen Li 1*
  • 1 Hunan University    
  • *corresponding author yucenli@hnu.edu.cn
Published on 21 February 2024 | https://doi.org/10.54254/2755-2721/39/20230602
ACE Vol.39
ISSN (Print): 2755-273X
ISSN (Online): 2755-2721
ISBN (Print): 978-1-83558-303-6
ISBN (Online): 978-1-83558-304-3

Abstract

As science and technology develop fast, people nowadays can have an easy approach to various advanced products. The use of Internet of Things has become a reality. To ensure its reliable implementation in daily life, stable and efficient hardware equipment like sensor is essential, where absolute value detector is widely used. A detector is created on the basis of this. The circuit can compare a signed 6-bit number with the threshold of a 5-bit number. This design uses MOS and pass-transistor logic (PLT) structure as the basic parts to form the transcoding logic and the subtraction logic. This paper also discusses the optimization of its minimum latency and energy usage based on logic effort parameters. In order to match a sequence of minimum delays, the article gives various power supply voltages and calculates each scheme’s lowest energy consumption for each voltage. The reduction of the energy cost is significant, which means the circuit has application value in reality. Besides, the different results are listed in a scatterplot to find out the trend of optimization, which may be helpful for selecting a proper scheme in the real program.

Keywords:

Absolute Value Detector, Delay, Energy Consumption, Optimization, Logic Effort

Li,Y. (2024). A 6-bit absolute value detector based on MOSFET and PTL structure. Applied and Computational Engineering,39,209-217.
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References

[1]. Paul, A., & Jeyaraj, R. (2019). Internet of Things: A primer. Human Behavior and Emerging Technologies, 1(1), 37–47.

[2]. Sanjeevi, P., Prasanna, S., Siva Kumar, B., Gunasekaran, G., Alagiri, I., & Vijay Anand, R. (2020). Precision agriculture and farming using Internet of Things based on wireless sensor network. Transactions on Emerging Telecommunications Technologies, 31(12).

[3]. Liu, Y., & Sanjev Dhakal. (2020). Internet of Things technology in mineral remote sensing monitoring. International Journal of Circuit Theory and Applications, 48(12), 2065–2077.

[4]. Vasco Lopes, N. (2020). Internet of Things feasibility for disabled people. Transactions on Emerging Telecommunications Technologies, 31(12), e3906.

[5]. Iranmanesh, S., Raikos, G., Jiang, Z., & Rodriguez-Villegas, E. (2016, June 1). CMOS implementation of a low power absolute value comparator circuit. IEEE Xplore.

[6]. Kumngern, M. (2013). Absolute Value Circuit for Biological Signal Processing Applications. 2013 4th International Conference on Intelligent Systems, Modelling and Simulation.

[7]. Sadeghi, A., Nabiollah Shiri, Mahmood Rafiee, & Rahim Ghayour. (2022). Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell. IET Circuits, Devices & Systems, 16(6), 437–460.

[8]. Hamid Tavakolaee, Gholamreza Ardeshir, & Yasser Baleghi. (2023). Design and analysis of a novel fast adder using logical effort method. Iet Computers and Digital Techniques, 17(3-4), 195–208.

[9]. Olivieri, M., Menichelli, F., & Mastrandrea, A. (2017). Optimal pipeline stage balancing in the presence of large isolated interconnect delay. Electronics Letters, 53(4), 229–231.

[10]. Alioto, M., Consoli, E., & Palumbo, G. (2011). From energy-delay metrics to constraints on the design of digital circuits. International Journal of Circuit Theory and Applications, 40(8), 815–834.

Cite this article

Li,Y. (2024). A 6-bit absolute value detector based on MOSFET and PTL structure. Applied and Computational Engineering,39,209-217.

Data availability

The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.

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About volume

Volume title: Proceedings of the 2023 International Conference on Machine Learning and Automation

ISBN：978-1-83558-303-6(Print) / 978-1-83558-304-3(Online)
Editor：Mustafa İSTANBULLU
Conference website: https://2023.confmla.org/
Conference date: 18 October 2023
Series: Applied and Computational Engineering
Volume number: Vol.39
ISSN：2755-2721(Print) / 2755-273X(Online)

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References

[1]. Paul, A., & Jeyaraj, R. (2019). Internet of Things: A primer. Human Behavior and Emerging Technologies, 1(1), 37–47.

[2]. Sanjeevi, P., Prasanna, S., Siva Kumar, B., Gunasekaran, G., Alagiri, I., & Vijay Anand, R. (2020). Precision agriculture and farming using Internet of Things based on wireless sensor network. Transactions on Emerging Telecommunications Technologies, 31(12).

[3]. Liu, Y., & Sanjev Dhakal. (2020). Internet of Things technology in mineral remote sensing monitoring. International Journal of Circuit Theory and Applications, 48(12), 2065–2077.

[4]. Vasco Lopes, N. (2020). Internet of Things feasibility for disabled people. Transactions on Emerging Telecommunications Technologies, 31(12), e3906.

[5]. Iranmanesh, S., Raikos, G., Jiang, Z., & Rodriguez-Villegas, E. (2016, June 1). CMOS implementation of a low power absolute value comparator circuit. IEEE Xplore.

[6]. Kumngern, M. (2013). Absolute Value Circuit for Biological Signal Processing Applications. 2013 4th International Conference on Intelligent Systems, Modelling and Simulation.

[7]. Sadeghi, A., Nabiollah Shiri, Mahmood Rafiee, & Rahim Ghayour. (2022). Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell. IET Circuits, Devices & Systems, 16(6), 437–460.

[8]. Hamid Tavakolaee, Gholamreza Ardeshir, & Yasser Baleghi. (2023). Design and analysis of a novel fast adder using logical effort method. Iet Computers and Digital Techniques, 17(3-4), 195–208.

[9]. Olivieri, M., Menichelli, F., & Mastrandrea, A. (2017). Optimal pipeline stage balancing in the presence of large isolated interconnect delay. Electronics Letters, 53(4), 229–231.

[10]. Alioto, M., Consoli, E., & Palumbo, G. (2011). From energy-delay metrics to constraints on the design of digital circuits. International Journal of Circuit Theory and Applications, 40(8), 815–834.

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