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A Study of Advances in Asynchronous FIFO Design
- 1 School of Physics, Xi'an Jiaotong University, Xi’an, China
* Author to whom correspondence should be addressed.
Abstract
With the continuous development of the new generation of microelectronics, there are several different clock domains in the complex digital systems. In order to iron out the complications caused by data transfer and storage in different clock domains, the designer used asynchronous FIFO (first in first out) in the design to realize cross-clock communication, data buffer. By analyzing and studying a number of results on asynchronous FIFO, this paper provides a comprehensive overview of the results of asynchronous FIFO up to now. This paper mainly summarizes the study of using Gray code to solve the substable problem in asynchronous FIFO, using the empty-full flag bit technique for the empty-full judgment of reading and writing, and summarizes how to make the structure of cyclic Asynchronous FIFO, and regulating the Asynchronous FIFO depth to improve their performance. For the practical application of asynchronous FIFO-based, this paper summarizes the optimization techniques of UART communication protocol based on asynchronous FIFO. the use of handshake signals for asynchronous FIFO design based on handshake-synchronous cross-clock-domain transmission technology is also a widely used technique for asynchronous FIFO.
Keywords
Asynchronous FIFO, Cross Clock Domain Processing, Verilog, Buffers, Synchronizers, Substable
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Cite this article
Wang,Q. (2025). A Study of Advances in Asynchronous FIFO Design. Applied and Computational Engineering,121,14-23.
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