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Published on 30 May 2023
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Lei,X. (2023). Review on the FPGA design optimization for ASIC. Applied and Computational Engineering,4,524-531.
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Review on the FPGA design optimization for ASIC

Xiaohaoyang Lei *,1,
  • 1 School of Intelligent Engineering, Xi’an Jiaotong-liverpool University, SuZhou, JiangSu, 215123, China

* Author to whom correspondence should be addressed.

https://doi.org/10.54254/2755-2721/4/2023317

Abstract

FPGA is a product of further development on programmable devices such as PAL and GAL. It is not only a chip, but a design pattern. With the rapid growth in FPGA performance and density, its complete top-down model can be applied to the development of similar ASICs while improving the technology itself. This paper shows that a summary analysis of previous articles can conclude that the application of FPGA design to ASICs can lead to optimization of many aspects. Architecture-level embedding and mapping transformation are the current mainstream application methods, both of which can bring strong economic and time benefits. Meanwhile, there are various issues that need special consideration in the application process which is related to the question of whether or not to map and convert. Finally, according to the analysis, we still need to solve two important issues which are the lack of automatic mapping tools and the lack of a unified function library in the future.

Keywords

FPGA, ASIC, VHDL, hardware description language, architecture hierarchy embedding

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Cite this article

Lei,X. (2023). Review on the FPGA design optimization for ASIC. Applied and Computational Engineering,4,524-531.

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About volume

Volume title: Proceedings of the 3rd International Conference on Signal Processing and Machine Learning

Conference website: http://www.confspml.org
ISBN:978-1-915371-55-3(Print) / 978-1-915371-56-0(Online)
Conference date: 25 February 2023
Editor:Omer Burak Istanbullu
Series: Applied and Computational Engineering
Volume number: Vol.4
ISSN:2755-2721(Print) / 2755-273X(Online)

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