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A High-Performance CMOS Operational Amplifier Design
- 1 Nanjing University of Information Science and Technology
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Abstract
This paper presents the design of a high-performance two-stage folded cascode operational amplifier based on the TSMC 180nm CMOS process. The input stage adopts a folded cascode structure, which not only achieves a high DC gain but also enhances the suppression of common-mode noise. The output stage uses a common-source structure to ensure the output swing. To ensure the stability of the operational amplifier, a Miller capacitor is used to compensate the output stage amplifier, ensuring sufficient phase margin. The design and simulation of the circuit were completed using Cadence software. Simulation results under a 1.8V supply voltage and a 2pF load capacitance show that the DC gain of the operational amplifier is no less than 84dB, the common-mode rejection ratio (CMRR) is greater than 130dB, and the power supply rejection ratio (PSRR) is greater than 114dB under various temperature and process corners. At room temperature, the quiescent power consumption is 1.5mW, and the circuit demonstrates good robustness. The circuit has low power consumption and has significant application value in bandgap reference circuits and active filter circuits.
Keywords
TSMC 180nm, operational amplifier, common-mode rejection ratio, power supply rejection ratio
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Cite this article
Yao,P. (2025). A High-Performance CMOS Operational Amplifier Design. Applied and Computational Engineering,147,197-202.
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Volume title: Proceedings of the 3rd International Conference on Mechatronics and Smart Systems
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