References
[1]. A. WIlliams. 2019. LARGEST CHIP EVER HOLDS 1.2 TRILLION TRANSISTORS. Retrieved April 5, 2022
[2]. L. Wang and M. Luo, "Machine Learning Applications and Opportunities in IC Design Flow," 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2019, pp. 1-3, doi: 10.1109/VLSI-DAT.2019.8742073.
[3]. S. A. Beheshti-Shirazi, A. Vakil, S. Manoj, I. Savidis, H. Homayoun, and A. Sasan, “A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop,” in Proceedings of the 2021 on Great Lakes Symposium on VLSI, in GLSVLSI ’21. New York, NY, USA: Association for Computing Machinery, 2021, pp. 181–187. doi: 10.1145/3453688.3461754.
[4]. R. Samanta, J. Hu and P. Li, "Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, pp. 1025-1035, July 2010, doi: 10.1109/TVLSI.2009.2019088.
[5]. Y. Kwon, J. Jung, I. Han and Y. Shin, "Transient Clock Power Estimation of Pre-CTS Netlist," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-4, doi: 10.1109/ISCAS.2018.8351430.
[6]. S. Nagaria and S. Deb, "Designing of an Optimization Technique for the Prediction of CTS Outcomes using Neural Network," 2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Chennai, India, 2020, pp. 312-315, doi: 10.1109/iSES50453.2020.00075.
[7]. Y.-C. Lu, J. Lee, A. Agnesina, K. Samadi, and S. Lim, "GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization," Nov. 2019, pp. 1–8. doi: 10.1109/ICCAD45719.2019.8942063.
[8]. Y. Lin et al., "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 4, pp. 748-761, April 2021, doi: 10.1109/TCAD.2020.3003843.
[9]. A. Agnesina, K. Chang and S. K. Lim, "VLSI Placement Parameter Optimization using Deep Reinforcement Learning," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-9.
[10]. R. Cheng and J. Yan, "On Joint Learning for Solving Placement and Routing in Chip Design," in Advances in Neural Information Processing Systems, M. Ranzato, A. Beygelzimer, Y. Dauphin, P. S. Liang, and J. W. Vaughan, Eds., Curran Associates, Inc., 2021, pp. 16508–16519.
[11]. W. -K. Cheng, Y. -Y. Guo and C. -S. Wu, "Evaluation of routability-driven macro placement with machine-learning technique," 2018 7th International Symposium on Next Generation Electronics (ISNE), Taipei, Taiwan, 2018, pp. 1-3, doi: 10.1109/ISNE.2018.8394712.
[12]. Y. Lin, T. Qu, Z. Lu, Y. Su and Y. Wei, "Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 9, pp. 3132-3142, Sept. 2022, doi: 10.1109/TCAD.2021.3117505.
[13]. (IR)IR Drop Analysis in Physical Design | IR Analysis in VLSI. (2020, May 2). IR Drop Analysis in Physical Design | IR Analysis in VLSI. https://teamvlsi.com/2020/07/ir-analysis-in-asic-design-effects-and.html
[14]. T. -Y. Wu, S. Gharahi and J. A. Abraham, "An area efficient on-chip static IR drop detector/evaluator," 2009 IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, 2009, pp. 2009-2012, doi: 10.1109/ISCAS.2009.5118186.
[15]. V. A. Chhabria, Y. Zhang, H. Ren, B. Keller, B. Khailany and S. S. Sapatnekar, "MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021, pp. 1825-1828, doi: 10.23919/DATE51398.2021.9473914.
[16]. P. Huang, C. Ma, and Z. Wu, "Fast Dynamic IR-Drop Prediction Using Machine Learning in Bulk FinFET Technologies," Symmetry, vol. 13, no. 10, p. 1807, Sep. 2021, doi: 10.3390/sym13101807.
[17]. Z. Xie et al., "PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network," 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, 2020, pp. 13-18, doi: 10.1109/ASP-DAC47756.2020.9045574.
[18]. S. Bian, M. Shintani, M. Hiromoto, and T. Sato, "LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations," in Proceedings of the 54th Annual Design Automation Conference 2017, in DAC ’17. New York, NY, USA: Association for Computing Machinery, 2017. doi: 10.1145/3061639.3062280.
[19]. T. Sharma, S. Kolluru, and K. S. Stevens, "Learning Based Timing Closure on Relative Timed Design," in VLSI-SoC: Design Trends, A. Calimera, P.-E. Gaillardon, K. Korgaonkar, S. Kvatinsky, and R. Reis, Eds., Cham: Springer International Publishing, 2021, pp. 133–148..
[20]. T. Yang, G. He and P. Cao, "Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework," 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, 2022, pp. 184-189, doi: 10.1109/ASP-DAC52403.2022.9712484.
Cite this article
Yu,J.;Li,Y.;Liu,X.;Yang,Z. (2023). Machine learning in physical design. Theoretical and Natural Science,28,144-150.
Data availability
The datasets used and/or analyzed during the current study will be available from the authors upon reasonable request.
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References
[1]. A. WIlliams. 2019. LARGEST CHIP EVER HOLDS 1.2 TRILLION TRANSISTORS. Retrieved April 5, 2022
[2]. L. Wang and M. Luo, "Machine Learning Applications and Opportunities in IC Design Flow," 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2019, pp. 1-3, doi: 10.1109/VLSI-DAT.2019.8742073.
[3]. S. A. Beheshti-Shirazi, A. Vakil, S. Manoj, I. Savidis, H. Homayoun, and A. Sasan, “A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop,” in Proceedings of the 2021 on Great Lakes Symposium on VLSI, in GLSVLSI ’21. New York, NY, USA: Association for Computing Machinery, 2021, pp. 181–187. doi: 10.1145/3453688.3461754.
[4]. R. Samanta, J. Hu and P. Li, "Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, pp. 1025-1035, July 2010, doi: 10.1109/TVLSI.2009.2019088.
[5]. Y. Kwon, J. Jung, I. Han and Y. Shin, "Transient Clock Power Estimation of Pre-CTS Netlist," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-4, doi: 10.1109/ISCAS.2018.8351430.
[6]. S. Nagaria and S. Deb, "Designing of an Optimization Technique for the Prediction of CTS Outcomes using Neural Network," 2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Chennai, India, 2020, pp. 312-315, doi: 10.1109/iSES50453.2020.00075.
[7]. Y.-C. Lu, J. Lee, A. Agnesina, K. Samadi, and S. Lim, "GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization," Nov. 2019, pp. 1–8. doi: 10.1109/ICCAD45719.2019.8942063.
[8]. Y. Lin et al., "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 4, pp. 748-761, April 2021, doi: 10.1109/TCAD.2020.3003843.
[9]. A. Agnesina, K. Chang and S. K. Lim, "VLSI Placement Parameter Optimization using Deep Reinforcement Learning," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-9.
[10]. R. Cheng and J. Yan, "On Joint Learning for Solving Placement and Routing in Chip Design," in Advances in Neural Information Processing Systems, M. Ranzato, A. Beygelzimer, Y. Dauphin, P. S. Liang, and J. W. Vaughan, Eds., Curran Associates, Inc., 2021, pp. 16508–16519.
[11]. W. -K. Cheng, Y. -Y. Guo and C. -S. Wu, "Evaluation of routability-driven macro placement with machine-learning technique," 2018 7th International Symposium on Next Generation Electronics (ISNE), Taipei, Taiwan, 2018, pp. 1-3, doi: 10.1109/ISNE.2018.8394712.
[12]. Y. Lin, T. Qu, Z. Lu, Y. Su and Y. Wei, "Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 9, pp. 3132-3142, Sept. 2022, doi: 10.1109/TCAD.2021.3117505.
[13]. (IR)IR Drop Analysis in Physical Design | IR Analysis in VLSI. (2020, May 2). IR Drop Analysis in Physical Design | IR Analysis in VLSI. https://teamvlsi.com/2020/07/ir-analysis-in-asic-design-effects-and.html
[14]. T. -Y. Wu, S. Gharahi and J. A. Abraham, "An area efficient on-chip static IR drop detector/evaluator," 2009 IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, 2009, pp. 2009-2012, doi: 10.1109/ISCAS.2009.5118186.
[15]. V. A. Chhabria, Y. Zhang, H. Ren, B. Keller, B. Khailany and S. S. Sapatnekar, "MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021, pp. 1825-1828, doi: 10.23919/DATE51398.2021.9473914.
[16]. P. Huang, C. Ma, and Z. Wu, "Fast Dynamic IR-Drop Prediction Using Machine Learning in Bulk FinFET Technologies," Symmetry, vol. 13, no. 10, p. 1807, Sep. 2021, doi: 10.3390/sym13101807.
[17]. Z. Xie et al., "PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network," 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, 2020, pp. 13-18, doi: 10.1109/ASP-DAC47756.2020.9045574.
[18]. S. Bian, M. Shintani, M. Hiromoto, and T. Sato, "LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations," in Proceedings of the 54th Annual Design Automation Conference 2017, in DAC ’17. New York, NY, USA: Association for Computing Machinery, 2017. doi: 10.1145/3061639.3062280.
[19]. T. Sharma, S. Kolluru, and K. S. Stevens, "Learning Based Timing Closure on Relative Timed Design," in VLSI-SoC: Design Trends, A. Calimera, P.-E. Gaillardon, K. Korgaonkar, S. Kvatinsky, and R. Reis, Eds., Cham: Springer International Publishing, 2021, pp. 133–148..
[20]. T. Yang, G. He and P. Cao, "Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework," 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, 2022, pp. 184-189, doi: 10.1109/ASP-DAC52403.2022.9712484.